[Skiboot] [PATCH v3 2/3] npu2: Enable recoverable data link (no-stall) interrupts

[Alistair Popple]

> 
> This is really close to the setup we do for opencapi and it looks good 
> to me. The only difference really is that there are more interrupts 
> supported for opencapi (35 instead of 23), so the alignment requirement 
> when allocating the IPIs is different (64 instead of 32). But that 
> shouldn't be your concern.

I am ok for someone to investigate if we can share the setup (NVLink and OCAPI
are so similar that it makes sense to share as much code as possible imho).
However we need this upstream "yesterday" so lets leave that for now. Thanks
Sam!

Acked-By: Alistair Popple <alistair at popple.id.au>

> Andrew: with your refactoring of the opencapi code to support multiple 
> devices, we need to (re)discuss if it's workable to mix opencapi and 
> nvlink devices under the same PHB. I think the latest was that they 
> would have to be on 2 different PHYs, but is that even ok? We can 
> discuss it on Wednesday.
> 
>    Fred
> 
> 
> 
> >   static void npu2_create_phb(struct dt_node *dn)
> >   {
> >   	const struct dt_property *prop;
> > @@ -1678,7 +1782,9 @@ static void npu2_create_phb(struct dt_node *dn)
> >   	list_head_init(&p->phb.devices);
> >   	list_head_init(&p->phb.virt_devices);
> > 
> > +	npu2_setup_irqs(p);
> >   	npu2_populate_devices(p, dn);
> > +	npu2_add_interrupt_map(p, dn);
> >   	npu2_add_phb_properties(p);
> > 
> >   	slot = npu2_slot_create(&p->phb);
> > diff --git a/include/npu2-regs.h b/include/npu2-regs.h
> > index 86e2658a..759404cc 100644
> > --- a/include/npu2-regs.h
> > +++ b/include/npu2-regs.h
> > @@ -286,6 +286,16 @@ void npu2_write_mask(struct npu2 *p, uint64_t reg, uint64_t val, uint64_t mask);
> >   #define NPU2_MISC_ERR_RPT_HOLD			NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_MISC, 0x020)
> >   #define NPU2_MISC_ERR_RPT_MASK			NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_MISC, 0x028)
> >   #define NPU2_MISC_CFG				NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_MISC, 0x030)
> > +#define   NPU2_MISC_CFG_CONFIG_SYNC_WAIT	PPC_BITMASK(0,4)
> > +#define   NPU2_MISC_CFG_PERF_CONFIG_ENABLE	PPC_BIT(5)
> > +#define   NPU2_MISC_CFG_PERF_CONFIG_PE_MASK	PPC_BIT(6)
> > +#define   NPU2_MISC_CFG_PERF_CONFIG_PE_MATCH	PPC_BITMASK(7,10)
> > +#define   NPU2_MISC_CFG_IPI_PS			PPC_BIT(11)
> > +#define   NPU2_MISC_CFG_IPI_PS_4K		0
> > +#define   NPU2_MISC_CFG_IPI_PS_64K		1
> > +#define   NPU2_MISC_CFG_IPI_OS			PPC_BIT(12)
> > +#define   NPU2_MISC_CFG_IPI_OS_AIX		0
> > +#define   NPU2_MISC_CFG_IPI_OS_LINUX		1
> >   #define NPU2_MISC_INHIBIT_CFG			NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_MISC, 0x038)
> >   #define NPU2_MISC_FREEZE_ENABLE0		NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_MISC, 0x040)
> >   #define NPU2_MISC_FREEZE_ENABLE1		NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_MISC, 0x048)
> > 
> 
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