[Skiboot] [PATCH] npu2: hw-procedures: Enable low power mode

[Reza Arbab]

Add a procedure which sets the NTL low power config register.

Signed-off-by: Reza Arbab <arbab at linux.vnet.ibm.com>
---
 hw/npu2-hw-procedures.c | 18 +++++++++++++++++-
 include/npu2-regs.h     |  6 ++++++
 2 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/hw/npu2-hw-procedures.c b/hw/npu2-hw-procedures.c
index a140aed..24feb03 100644
--- a/hw/npu2-hw-procedures.c
+++ b/hw/npu2-hw-procedures.c
@@ -310,9 +310,25 @@ static uint32_t phy_reset_complete(struct npu2_dev *ndev)
 		phy_write_lane(ndev, &NPU2_PHY_TX_LANE_PDWN, lane, 0);
 	}
 
+	return PROCEDURE_NEXT;
+}
+
+/* Procedure 1.2.11 - Enable Low Power Mode */
+static uint32_t enable_low_power(struct npu2_dev *ndev)
+{
+	uint64_t val;
+
+	val = SETFIELD(NPU2_NTL_LOW_POWER_CFG_MODE_ENABLE, 0ull, 1);
+	val = SETFIELD(NPU2_NTL_LOW_POWER_CFG_TIMER_TICK_CONFIG, val, 1);
+	val = SETFIELD(NPU2_NTL_LOW_POWER_CFG_MIN_CRED_THRESH, val, 8);
+	val = SETFIELD(NPU2_NTL_LOW_POWER_CFG_MAX_CRED_THRESH, val, 15);
+	val = SETFIELD(NPU2_NTL_LOW_POWER_CFG_CNT_THRESH, val, 8);
+	npu2_write(ndev->npu, NPU2_NTL_LOW_POWER_CFG(ndev), val);
+
 	return PROCEDURE_COMPLETE;
 }
-DEFINE_PROCEDURE(phy_reset, phy_reset_wait, phy_reset_complete);
+DEFINE_PROCEDURE(phy_reset, phy_reset_wait, phy_reset_complete,
+		 enable_low_power);
 
 /* Procedure 1.2.6 - I/O PHY Tx Impedance Calibration */
 static uint32_t phy_tx_zcal(struct npu2_dev *ndev)
diff --git a/include/npu2-regs.h b/include/npu2-regs.h
index 86e2658..24d8549 100644
--- a/include/npu2-regs.h
+++ b/include/npu2-regs.h
@@ -248,6 +248,12 @@ void npu2_write_mask(struct npu2 *p, uint64_t reg, uint64_t val, uint64_t mask);
 #define NPU2_NTL_MISC_CFG1(ndev)		NPU2_NTLU_REG_OFFSET(ndev, 0x0C0)
 #define NPU2_NTL_SCRATCH1(ndev)			NPU2_NTLU_REG_OFFSET(ndev, 0x0D0)
 #define NPU2_NTL_LOW_POWER_CFG(ndev)		NPU2_NTLU_REG_OFFSET(ndev, 0x0E0)
+#define   NPU2_NTL_LOW_POWER_CFG_MODE_ENABLE		PPC_BIT(0)
+#define   NPU2_NTL_LOW_POWER_CFG_ONLY_MODE		PPC_BIT(1)
+#define   NPU2_NTL_LOW_POWER_CFG_TIMER_TICK_CONFIG	PPC_BITMASK(2,7)
+#define   NPU2_NTL_LOW_POWER_CFG_MIN_CRED_THRESH	PPC_BITMASK(8,19)
+#define   NPU2_NTL_LOW_POWER_CFG_MAX_CRED_THRESH	PPC_BITMASK(20,31)
+#define   NPU2_NTL_LOW_POWER_CFG_CNT_THRESH		PPC_BITMASK(32,43)
 #define NPU2_NTL_DBG_INHIBIT_CFG(ndev)		NPU2_NTL_REG_OFFSET(ndev, 0x220)
 #define NPU2_NTL_DISPLAY_CTL(ndev)		NPU2_NTL_REG_OFFSET(ndev, 0x280)
 #define NPU2_NTL_DISPLAY_DATA0(ndev)		NPU2_NTL_REG_OFFSET(ndev, 0x288)
-- 
1.8.3.1