[Skiboot] [PATCH v6 6/9] vas: Create MMIO device tree node

[Sukadev Bhattiprolu]

Create a device tree node for VAS and add properties that Linux
will need to configure/use VAS.

Signed-off-by: Sukadev Bhattiprolu <sukadev at linux.vnet.ibm.com>
---

Changelog[v6]:
	- [Ben Herrenschmidt]: Create the MMIO dt node in dt_root (as
	  a platform dev) rather than under xscom. Update reg properties
	  to export paste base address and paste window id bit field.

	- [Michael Neuling] Use the new phys_map_get() interface rather
	  than macros for the MMIO addresses.

Changelog[v5]:
	[Stewart Smith] Add a compatible "ibm,vas" property and document
	device tree entries.

	[Michael Neuling] Rather than having separate properties for
	HVWC, UWC and window address, make them all "reg" properties.
---
 core/vas.c              | 30 ++++++++++++++++++++++++++++++
 doc/device-tree/vas.rst | 28 ++++++++++++++++++++++++++++
 2 files changed, 58 insertions(+)
 create mode 100644 doc/device-tree/vas.rst

diff --git a/core/vas.c b/core/vas.c
index 0395749..cebda05 100644
--- a/core/vas.c
+++ b/core/vas.c
@@ -321,6 +321,34 @@ static struct vas *alloc_vas(uint32_t chip_id, uint32_t vas_id, uint64_t base)
 	return vas;
 }
 
+static void create_mm_dt_node(struct proc_chip *chip)
+{
+	struct dt_node *dn;
+	struct vas *vas;
+	uint64_t hvwc_start, hvwc_len;
+	uint64_t uwc_start, uwc_len;
+	uint64_t pbar_start, pbar_len;
+	uint64_t pbf_start, pbf_nbits;
+
+	vas = chip->vas;
+	get_hvwc_mmio_bar(chip->id, &hvwc_start, &hvwc_len);
+	get_uwc_mmio_bar(chip->id, &uwc_start, &uwc_len);
+	get_paste_bar(chip->id, &pbar_start, &pbar_len);
+	get_paste_bitfield(&pbf_start, &pbf_nbits);
+
+	dn = dt_new_addr(dt_root, "vas", hvwc_start);
+
+	dt_add_property_strings(dn, "compatible", "ibm,power9-vas",
+					"ibm,vas");
+
+	dt_add_property_u64s(dn, "reg", hvwc_start, hvwc_len,
+					uwc_start, uwc_len,
+					pbar_start, pbar_len,
+					pbf_start, pbf_nbits);
+
+	dt_add_property(dn, "ibm,vas-id", &vas->vas_id, sizeof(vas->vas_id));
+}
+
 /*
  * Disable one VAS instance.
  *
@@ -364,6 +392,8 @@ static int init_vas_inst(struct dt_node *np)
 	    			init_rma(chip))
 		return -1;
 
+	create_mm_dt_node(chip);
+
 	prlog(PR_INFO, "VAS: Initialized chip %d\n", chip->id);
 	return 0;
 
diff --git a/doc/device-tree/vas.rst b/doc/device-tree/vas.rst
new file mode 100644
index 0000000..606f476
--- /dev/null
+++ b/doc/device-tree/vas.rst
@@ -0,0 +1,28 @@
+Virtual Accelerator Switchboard (VAS)
+====================================
+
+VAS is present in P9 or later processors. In P9, each chip has one
+instance of VAS. Each instance of VAS is represented as a "platform
+device" i.e as a node in root of the device tree:
+::
+
+  /vas@<vas_addr>
+
+with unique VAS address which also represents the Hypervisor window
+context address for the instance of VAS.
+
+Each VAS node contains: ::
+
+  compatible: "ibm,power9-vas", "ibm,vas"
+  
+  ibm,vas-id: unique identifier for each instance of VAS in the system.
+
+  reg: contains 8 64-bit fields. 
+
+        Fields [0] and [1] represent the Hypervisor window context BAR
+        (start and length). Fields [2] and [3] represent the OS/User
+        window context BAR (start and length). Fields [4] and [5]
+        contain the start and length of paste power bus address region
+        for this chip. Fields [6] and [7] represent the bit field (start
+        bit and number of bits) where the window id of the window should
+        be encoded when computing the paste address for the window.
-- 
2.7.4