[Skiboot] [PATCH V3 3/5] capi: Enable capi mode

[Stewart Smith]

Frederic Barrat <fbarrat at linux.vnet.ibm.com> writes:
> Le 04/05/2017 à 17:57, Christophe Lombard a écrit :
>> Enable the Coherently attached processor interface. The PHB is used as
>> a CAPI interface.
>> CAPI Adapters can be connected to whether PEC0 or PEC2. Single port
>
>                                    ^ either?
>
> Also title of the commit should say it's for phb4.
>
>
>> CAPI adapter can be connected to either PEC0 or PEC2, but Dual-Port
>> Adapter can be only connected to PEC2
>>    CAPP0 attached to PHB0(PEC0 - single port)
>>    CAPP1 attached to PHB3(PEC2 - single or dual port)
>> As we did for PHB3, a new specific file 'phb4-capp.h' is created to
>> contain the CAPP register definitions.
>>
>> Signed-off-by: Christophe Lombard <clombard at linux.vnet.ibm.com>
>> ---
>>  core/cpu.c          |  17 +-
>>  hw/phb4.c           | 511 +++++++++++++++++++++++++++++++++++++++++++++++++++-
>>  include/chip.h      |   1 +
>>  include/opal-api.h  |   1 +
>>  include/phb4-capp.h |  60 ++++++
>>  include/phb4-regs.h |   7 +-
>>  include/phb4.h      |   1 +
>>  7 files changed, 591 insertions(+), 7 deletions(-)
>>  create mode 100644 include/phb4-capp.h
>>
>> diff --git a/core/cpu.c b/core/cpu.c
>> index c7e650d..a096d2f 100644
>> --- a/core/cpu.c
>> +++ b/core/cpu.c
>> @@ -1099,12 +1099,27 @@ static int64_t opal_reinit_cpus(uint64_t flags)
>>  opal_call(OPAL_REINIT_CPUS, opal_reinit_cpus, 1);
>>
>>  #define NMMU_XLAT_CTL_PTCR 0xb
>> +#define NMMU_XLAT_CTL_SMCR 0x12
>>  static int64_t nmmu_set_ptcr(uint64_t chip_id, struct dt_node *node, uint64_t ptcr)
>>  {
>>  	uint32_t nmmu_base_addr;
>> +	struct proc_chip *chip;
>> +	uint64_t reg;
>> +	int64_t rc;
>>
>>  	nmmu_base_addr = dt_get_address(node, 0, NULL);
>> -	return xscom_write(chip_id, nmmu_base_addr + NMMU_XLAT_CTL_PTCR, ptcr);
>> +	rc = xscom_write(chip_id, nmmu_base_addr + NMMU_XLAT_CTL_PTCR, ptcr);
>> +	if (!rc) {
>> +		/* Disable for Radix page-walk cache */
>> +		chip = get_chip(chip_id);
>> +		if ((chip->type == PROC_CHIP_P9_NIMBUS) ||
>> +		    (chip->type == PROC_CHIP_P9_CUMULUS)) {
>> +			xscom_read(chip_id, nmmu_base_addr + NMMU_XLAT_CTL_SMCR, &reg);
>> +			reg |= PPC_BIT(52);
>> +			xscom_write(chip_id, nmmu_base_addr + NMMU_XLAT_CTL_SMCR, reg);
>> +		}
>> +	}
>> +	return rc;
>>  }
>
> [ + Alistair for awareness ]
>
> It should be a separate patch on its own, to make it more visible.
> We had discussed it, but for the record: we need to limit the workaround 
> to DD1.x and DD2.0, as it will be fixed with DD2.1.
> Stewart can comment, but it looks like it can be tested with 
> chip->ec_level. From chip.h, it's encoded like:
> 	/* 0xMm (DD1.0 = 0x10) */

Yes, ec_level check is correct here. There's a bunch of examples
of checking it scattered throughout the tree.

>> +
>> +		if (!(p->flags & PHB4_CAPP_RECOVERY))
>> +			disable_capi_mode(p);
>
> Are we ready to support this? I guess that's a question to be sorted out 
> with the PSL team.
> disable_capi_mode() is mostly useful to support kexec(), which is 
> desirable, but I'm wondering if it's not a bit early.

It depends if anyone wants to be fixing bugs in it..... and if people
want/need to boot from CAPI2 adapters.

This also may affect fast-reboot (when we have it for p9)

-- 
Stewart Smith
OPAL Architect, IBM.