[Skiboot] [PATCH v11 10/11] skiboot: Add core IMC related counter configuration

[Stewart Smith]

Madhavan Srinivasan <maddy at linux.vnet.ibm.com> writes:
> diff --git a/hw/imc.c b/hw/imc.c
> index 4063b71cfeda..845d1b41a3a6 100644
> --- a/hw/imc.c
> +++ b/hw/imc.c
> @@ -282,26 +304,84 @@ err:
>  }
>
>  /*
> - * opal_imc_counters_init : This call initialize the IMC engine.
> - *
> + * opal_imc_counters_init : This call initializes core IMC Engine for the
> + *			    current core, by initializing the pdbars, htm_mode,
> + *			    and the event_mask.
>   * This call is not being used in case of NEST IMC.
> - * Additional arguments will be added to this call in the following patch.
>   */
> -static int64_t opal_imc_counters_init(uint32_t type)
> +static int64_t opal_imc_counters_init(uint32_t type, uint64_t addr)
>  {
> -	if (type == OPAL_IMC_COUNTERS_NEST)
> +	struct proc_chip *chip;
> +	int core_id, phys_core_id, ret = OPAL_SUCCESS;
> +
> +	switch (type) {
> +	case OPAL_IMC_COUNTERS_NEST:
>  		prerror("IMC: unknown operation for nest imc\n");
> +		break;
> +	case OPAL_IMC_COUNTERS_CORE:
> +		chip = get_chip(this_cpu()->chip_id);
> +		phys_core_id = cpu_get_core_index(this_cpu());
> +		core_id = phys_core_id % 4;
> +
> +		/*
> +		 * Core IMC hardware mandate initing of three scoms
> +		 * to enbale or disable of the Core IMC engine.
> +		 *
> +		 * PDBAR: Scom contains the real address to store per-core
> +		 *        counter data in memory along with other bits.
> +		 *
> +		 * EventMask: Scom contain bits to denote event to multiplex
> +		 *            at different MSR[HV PR] values, along with bits for
> +		 *            sampling duration.
> +		 *
> +		 * HTM Scom: scom to enable counter data movement to memory.
> +		 */
> +		ret = xscom_write(chip->id,
> +				XSCOM_ADDR_P9_EP(phys_core_id,
> +						pdbar_scom_index[core_id]),
> +				(u64)(CORE_IMC_PDBAR_MASK & addr));
> +		if (ret < 0) {
> +			prerror("IMC: error in xscom_write for pdbar\n");
> +			goto hw_err;
> +		}
> +
> +		ret = xscom_write(chip->id,
> +				XSCOM_ADDR_P9_EC(phys_core_id,
> +					 CORE_IMC_EVENT_MASK_ADDR),
> +				(u64)CORE_IMC_EVENT_MASK);
> +		if (ret < 0) {
> +			prerror("IMC: error in xscom_write for event mask\n");
> +			goto hw_err;
> +		}
> +
> +		ret = xscom_write(chip->id,
> +				XSCOM_ADDR_P9_EP(phys_core_id,
> +						htm_scom_index[core_id]),
> +				(u64)CORE_IMC_HTM_MODE_DISABLE);
> +		if (ret < 0) {
> +			prerror("IMC: error in xscom_write for htm mode\n");
> +			goto hw_err;
> +		}
> +
> +		break;

Is this sequence of SCOMs harmless to execute multiple times?

I'm thinking along kexec lines, where the first kernel inits IMC
counters (perhaps even uses them) and the second is going to want to do
the same.

(this should also be clearly documented in the OPAL API docs)

-- 
Stewart Smith
OPAL Architect, IBM.