[Skiboot] [RFC 3/4] SLW: Configure self-restore for HRMOR

[Oliver O'Halloran]

On Thu, May 4, 2017 at 5:16 PM, Akshay Adiga
<akshay.adiga at linux.vnet.ibm.com> wrote:
> Make a stop api call using libpore to restore HRMOR register. HRMOR needs
> to be cleared so that when thread exits stop, they arrives at linux
> system_reset vector (0x100).
>
> Signed-off-by: Akshay Adiga <akshay.adiga at linux.vnet.ibm.com>
> ---
>  hw/slw.c | 33 +++++++++++++++++++++++++++++++++
>  1 file changed, 33 insertions(+)
>
> diff --git a/hw/slw.c b/hw/slw.c
> index e4ab2c2..aeb8388 100644
> --- a/hw/slw.c
> +++ b/hw/slw.c
> @@ -1159,17 +1159,50 @@ static void slw_patch_regs(struct proc_chip *chip)
>                 /* XXX Add HIDs etc... */
>         }
>  }
> +
>  #endif /* __HAVE_LIBPORE__ */
>
>  static void slw_init_chip_p9(struct proc_chip *chip)
>  {
>         struct cpu_thread *c;
> +       int rc;
>
>         prlog(PR_NOTICE, "SLW: Init chip 0x%x\n", chip->id);
>
>         /* At power ON setup inits for power-mgt */
>         for_each_available_core_in_chip(c, chip->id)
>                 slw_set_overrides_p9(chip, c);
> +
> +       #if __HAVE_LIBPORE__
> +       if(!chip->homer_base) {
> +               log_simple_error(&e_info(OPAL_RC_SLW_REG),
> +                       "SLW: HOMER base not set %x\n",
> +                               chip->id);
> +               return;
> +       }
> +
> +       prlog(PR_NOTICE, "SLW: Configuring self-restore for HRMOR\n");
> +
> +       /* Should this be for_each_present_cpu() ? */
> +       for_each_available_cpu(c) {
> +
> +               if (c->chip_id != chip->id)
> +                       continue;
> +
> +               /*
> +                * Clear HRMOR. Need to update only for thread
> +                * 0 of each core. Doing it anyway for all threads
> +                */
> +               rc =  p9_stop_save_cpureg ((void *) chip->homer_base,
> +                                               P9_STOP_SPR_HRMOR, 0,
> +                                              c->pir);

Is it just HRMOR that needs to be setup by skiboot? The SPRs mentioned
in the code you pulled from hostboot are:

+    P9_STOP_SPR_DAWR    =    180,   // thread register
+    P9_STOP_SPR_HSPRG0  =    304,   // thread register
+    P9_STOP_SPR_HRMOR   =    313,   // core register
+    P9_STOP_SPR_LPCR    =    318,   // thread register
+    P9_STOP_SPR_HMEER   =    337,   // core register
+    P9_STOP_SPR_LDBAR   =    850,   // thread register
+    P9_STOP_SPR_PSSCR   =    855,   // thread register
+    P9_STOP_SPR_PMCR    =    884,   // core register
+    P9_STOP_SPR_HID     =   1008,   // core register
+    P9_STOP_SPR_MSR     =   2000,   // thread register

Which of these are setup by the kernel and which ones should we be
worrying about? Generally we want to keep code that touches the HID
register inside of skiboot, so should we be configuring a value for
that too?

> +               if (rc) {
> +                       log_simple_error(&e_info(OPAL_RC_SLW_REG),
> +                               "SLW: Failed to set HRMOR for CPU %x\n",
> +                               c->pir);
> +               }
> +       }
> +       #endif /* __HAVE_LIBPORE__ */
>  }
>  static void slw_init_chip(struct proc_chip *chip)
>  {
> --
> 2.5.5
>
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