[Skiboot] [PATCH] xive: Workaround a problem with indirect TM access

[Benjamin Herrenschmidt]

A HW issue can cause accesses to the content of the indirect data
area to pass the actual selection of the target thread. The
workaround is to read the PC_TCTXT_INDIR0 register back before
accessing the data area.

Signed-off-by: Benjamin Herrenschmidt <benh at kernel.crashing.org>
---
 hw/xive.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/hw/xive.c b/hw/xive.c
index 1952ce6..5a54730 100644
--- a/hw/xive.c
+++ b/hw/xive.c
@@ -3775,6 +3775,11 @@ static void xive_cleanup_cpu_tma(struct cpu_thread *c)
 		  PC_TCTXT_INDIR_VALID |
 		  SETFIELD(PC_TCTXT_INDIR_THRDID, 0ull, c->pir & 0xff));
 
+	/* Workaround for HW issue: Need to read the above register
+	 * back before doing the subsequent accesses
+	 */
+	xive_regr(x, PC_TCTXT_INDIR0);
+
 	/* Pull user context, OS context and Pool context if any */
 	in_be32(ind_tm_base + TM_SPC_PULL_USR_CTX);
 	in_be32(ind_tm_base + TM_SPC_PULL_OS_CTX);
@@ -4233,6 +4238,11 @@ static int64_t opal_xive_dump_tm(uint32_t offset, const char *n, uint32_t pir)
 		  PC_TCTXT_INDIR_VALID |
 		  SETFIELD(PC_TCTXT_INDIR_THRDID, 0ull, pir & 0xff));
 
+	/* Workaround for HW issue: Need to read the above register
+	 * back before doing the subsequent accesses
+	 */
+	xive_regr(x, PC_TCTXT_INDIR0);
+
 	v0 = in_be64(ind_tm_base + offset);
 	v1 = in_be64(ind_tm_base + offset + 8);
 	prlog(PR_INFO, "CPU[%04x]: TM state for QW %s\n", pir, n);
-- 
2.9.3