[Skiboot] [PATCH 0/3] P9 core dts support

Cédric Le Goater clg at kaod.org
Wed Mar 22 20:34:05 AEDT 2017

On 03/21/2017 10:30 PM, Stewart Smith wrote:
> Cédric Le Goater <clg at kaod.org> writes:
>> On 03/17/2017 12:51 AM, Stewart Smith wrote:
>>> Cédric Le Goater <clg at kaod.org> writes:
>>>> On 03/16/2017 08:07 AM, Stewart Smith wrote:
>>>>> Cédric Le Goater <clg at kaod.org> writes:
>>>>>> On 02/23/2017 07:04 PM, Rob Lippert wrote:
>>>>>>> On Thu, Feb 23, 2017 at 5:01 AM, Cédric Le Goater <clg at kaod.org> wrote:
>>>>>>>> Rob,
>>>>>>>> Some update,
>>>>>>>>>> Cedric, any update on getting the P9 DTS sensors to work with skiboot?
>>>>>>>>>> We have not tested yet since I was waiting for confirmation on your side.
>>>>>>>>> The skiboot framework is in place (with this patch) and the kernel
>>>>>>>>> module is creating the hwmon sysfs entries. I need to dig a little
>>>>>>>>> further to see why we read zeroes on the core DTS as I did not see
>>>>>>>>> any XSCOM errors.
>>>>>>>>> I will try on another system next week.
>>>>>>>> So it seems that the VPD in the OpenPOWER firmware misses calibration
>>>>>>>> settings for the core thermal latches. Those settings being zero
>>>>>>>> by default, the result of the equation is zero for the DTS.
>>>>>>>> I am working on getting these included in the VPD now.
>>>>>>> OK, will we need a VPD update for the CPU (which I don't think we can
>>>>>>> do) or just the planar VPD?
>>>>>> With a relatively recent firmware, I got it working on a 
>>>>>> witherspoon:
>>>>>> root at w39l:~#  cat  /sys/class/hwmon/hwmon0/temp*
>>>>>> 40000
>>>>>> Core 0
>>>>>> 54000
>>>>>> Core 4
>>>>>> 52000
>>>>>> Core 8
>>>>>> 49000
>>>>>> Core 12
>>>>>> 49000
>>>>>> Core 16
>>>>>> 50000
>>>>>> Core 20
>>>>>> root at w39l:~# sensors
>>>>>> ibmpowernv-isa-0000
>>>>>> Adapter: ISA adapter
>>>>>> Core 0:       +40.0°C  
>>>>>> Core 4:       +54.0°C  
>>>>>> Core 8:       +53.0°C  
>>>>>> Core 12:      +50.0°C  
>>>>>> Core 16:      +50.0°C  
>>>>>> Core 20:      +50.0°C  
>>>>>> Rob, I still need to check what exactly has changed in hostboot or if
>>>>>> I was testing on a really early version of the cores.  Anyhow, it is 
>>>>>> safe to use. 
>>>>>> Stewart, I think you can merge now.
>>>>> Thanks. It seemed to work on the zz I tried (at least if the test cases
>>>>> are correct... 
>>>> I gave it a try on a Romulus as well.
>>>>> might want to check with Pridhiviraj that we've got sufficient testing 
>>>>> in op-test-framework).
>>>> This looks correct :
>>>> https://github.com/open-power/op-test-framework/blob/master/testcases/OpTestSensors.py
>>>> May be we should look for specific OPAL sensors because if there is an
>>>> adapter exposing sensors on the system, the test will return success 
>>>> even if there are no OPAL.
>>> Yeah, I was thinking that.
>>> At this point, we *know* that we have some sensors inside the chip, and
>>> probably a relatively known set (or at least somewhat computable?), so
>>> yeah, we probably should check explicitly for them.
>>> I wonder if the list of sensors is constant enough to do what we do for
>>> PCI devices, have a per-machine file of sensors that we detected to
>>> ensure we continue to detect the correct ones.
>> We always have cores. So we could track these sensors. OpenPOWER systems
>> also expose the Centaur sensors.
> Yeah, I'm thinking the core sensors is where to go.
> Centaur sensors aren't necessarily going to be there in P9 though,
> right? Or do we have the same sensors but on die?

The SCOM registers for the memory controllers are defined but I haven't 
checked on a real system yet.

As for the others DTS, we have 2 more per quad (L3), so that makes 
an extra 12, and 3 more in the Nest chiplets. I think the nest ones 
cover N1-3 which are for the NPU and the memory controller interface.

And then, we have all the OCC ones on which Shilpasri is working. 


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