[Skiboot] [PATCH 3/3] platforms/astbmc/witherspoon.c: Add NPU2 slot mappings

[Alistair Popple]

For NVLink2 to function PCIe devices need to be associated with the right
NVLinks. This association is supposed to be passed down to Skiboot via HDAT but
those fields are still not correctly filled out. To work around this we add slot
tables for the NVLinks similar to what we have for P8+.

Signed-off-by: Alistair Popple <alistair at popple.id.au>
---
 platforms/astbmc/witherspoon.c | 272 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 272 insertions(+)

diff --git a/platforms/astbmc/witherspoon.c b/platforms/astbmc/witherspoon.c
index 4604986..6a77306 100644
--- a/platforms/astbmc/witherspoon.c
+++ b/platforms/astbmc/witherspoon.c
@@ -30,6 +30,273 @@
 
 #include "astbmc.h"
 
+static const struct slot_table_entry witherspoon_gpu0[] = {
+	{
+		.etype = st_pluggable_slot,
+		.location = ST_LOC_DEVFN(0x80,0),
+		.name = "GPU0",
+	},
+	{ .etype = st_end },
+};
+
+static const struct slot_table_entry witherspoon_gpu1[] = {
+	{
+		.etype = st_pluggable_slot,
+		.location = ST_LOC_DEVFN(0xa0,0),
+		.name = "GPU1",
+	},
+	{ .etype = st_end },
+};
+
+static const struct slot_table_entry witherspoon_gpu2[] = {
+	{
+		.etype = st_pluggable_slot,
+		.location = ST_LOC_DEVFN(0xc0,0),
+		.name = "GPU2",
+	},
+	{ .etype = st_end },
+};
+
+static const struct slot_table_entry witherspoon_gpu3[] = {
+	{
+		.etype = st_pluggable_slot,
+		.location = ST_LOC_DEVFN(0x60,0),
+		.name = "GPU3",
+	},
+	{ .etype = st_end },
+};
+
+static const struct slot_table_entry witherspoon_gpu4[] = {
+	{
+		.etype = st_pluggable_slot,
+		.location = ST_LOC_DEVFN(0x80,0),
+		.name = "GPU4",
+	},
+	{ .etype = st_end },
+};
+
+static const struct slot_table_entry witherspoon_gpu5[] = {
+	{
+		.etype = st_pluggable_slot,
+		.location = ST_LOC_DEVFN(0xa0,0),
+		.name = "GPU5",
+	},
+	{ .etype = st_end },
+};
+
+static const struct slot_table_entry witherspoon_plx0_down[] = {
+	{
+		.etype = st_builtin_dev,
+		.location = ST_LOC_DEVFN(0x4a,0),
+		.children = witherspoon_gpu0,
+		.name = "GPU0 down",
+	},
+	{
+		.etype = st_builtin_dev,
+		.location = ST_LOC_DEVFN(0x4b,0),
+		.children = witherspoon_gpu1,
+		.name = "GPU1 down",
+	},
+	{
+		.etype = st_builtin_dev,
+		.location = ST_LOC_DEVFN(0x4c,0),
+		.children = witherspoon_gpu2,
+		.name = "GPU2 down",
+	},
+	{ .etype = st_end },
+};
+
+static const struct slot_table_entry witherspoon_plx1_down[] = {
+	{
+		.etype = st_builtin_dev,
+		.location = ST_LOC_DEVFN(0x44,0),
+		.children = witherspoon_gpu3,
+		.name = "GPU3 down",
+	},
+	{
+		.etype = st_builtin_dev,
+		.location = ST_LOC_DEVFN(0x45,0),
+		.children = witherspoon_gpu4,
+		.name = "GPU4 down",
+	},
+	{
+		.etype = st_builtin_dev,
+		.location = ST_LOC_DEVFN(0x4d,0),
+		.children = witherspoon_gpu5,
+		.name = "GPU5 down",
+	},
+	{ .etype = st_end },
+};
+
+static const struct slot_table_entry witherspoon_plx0_up[] = {
+	{
+		.etype = st_builtin_dev,
+		.location = ST_LOC_DEVFN(0x20,0),
+		.children = witherspoon_plx0_down,
+	},
+	{ .etype = st_end },
+};
+
+static const struct slot_table_entry witherspoon_plx1_up[] = {
+	{
+		.etype = st_builtin_dev,
+		.location = ST_LOC_DEVFN(0x20,0),
+		.children = witherspoon_plx1_down,
+	},
+	{ .etype = st_end },
+};
+
+static const struct slot_table_entry witherspoon_phb0_4_slot[] = {
+	{
+		.etype = st_builtin_dev,
+		.location = ST_LOC_DEVFN(0,0),
+		.children = witherspoon_plx0_up,
+	},
+	{ .etype = st_end },
+};
+
+static const struct slot_table_entry witherspoon_phb8_5_slot[] = {
+	{
+		.etype = st_builtin_dev,
+		.location = ST_LOC_DEVFN(0,0),
+		.children = witherspoon_plx1_up,
+	},
+	{ .etype = st_end },
+};
+
+static const struct slot_table_entry witherspoon_npu0_slots[] = {
+	{
+		.etype = st_npu_slot,
+		.location = ST_LOC_NPU_GROUP(0),
+		.name = "GPU0",
+	},
+	{
+		.etype = st_npu_slot,
+		.location = ST_LOC_NPU_GROUP(1),
+		.name = "GPU1",
+	},
+	{
+		.etype = st_npu_slot,
+		.location = ST_LOC_NPU_GROUP(2),
+		.name = "GPU2",
+	},
+	{ .etype = st_end },
+};
+
+static const struct slot_table_entry witherspoon_npu8_slots[] = {
+	{
+		.etype = st_npu_slot,
+		.location = ST_LOC_NPU_GROUP(0),
+		.name = "GPU3",
+	},
+	{
+		.etype = st_npu_slot,
+		.location = ST_LOC_NPU_GROUP(1),
+		.name = "GPU4",
+	},
+	{
+		.etype = st_npu_slot,
+		.location = ST_LOC_NPU_GROUP(2),
+		.name = "GPU5",
+	},
+	{ .etype = st_end },
+};
+
+static const struct slot_table_entry witherspoon_phb_table[] = {
+	{
+		.etype = st_phb,
+		.location = ST_LOC_PHB(0,4),
+		.children = witherspoon_phb0_4_slot,
+	},
+	{
+		.etype = st_phb,
+		.location = ST_LOC_PHB(0,7),
+		.children = witherspoon_npu0_slots,
+	},
+	{
+		.etype = st_phb,
+		.location = ST_LOC_PHB(8,5),
+		.children = witherspoon_phb8_5_slot,
+	},
+	{
+		.etype = st_phb,
+		.location = ST_LOC_PHB(8,8),
+		.children = witherspoon_npu8_slots,
+	},
+	{ .etype = st_end },
+};
+
+#define NPU_BASE 0x5011000
+#define NPU_SIZE 0x2c
+#define NPU_INDIRECT0	0x8000000009010c3f
+#define NPU_INDIRECT1	0x800000000c010c3f
+
+static void create_link(struct dt_node *npu, int group, int index)
+{
+	struct dt_node *link;
+	uint32_t lane_mask;
+	uint64_t phy;
+	char namebuf[32];
+
+	snprintf(namebuf, sizeof(namebuf), "link@%x", index);
+	link = dt_new(npu, namebuf);
+
+	dt_add_property_string(link, "compatible", "ibm,npu-link");
+	dt_add_property_cells(link, "ibm,npu-link-index", index);
+
+	if (!(index / 3))
+		phy = NPU_INDIRECT0;
+	else
+		phy = NPU_INDIRECT1;
+
+	switch (index % 3) {
+	case 0:
+		lane_mask = 0xf1e000;
+		break;
+
+	case 1:
+		lane_mask = 0x0e1870;
+		break;
+
+	case 2:
+		lane_mask = 0x00078f;
+		break;
+
+	default:
+		assert(0);
+	}
+
+	dt_add_property_u64s(link, "ibm,npu-phy", phy);
+	dt_add_property_cells(link, "ibm,npu-lane-mask", lane_mask);
+	dt_add_property_cells(link, "ibm,npu-group-id", group);
+}
+
+static void dt_create_npu2(void)
+{
+        struct dt_node *xscom, *npu;
+        char namebuf[32];
+	int phb_index = 7;
+	int npu_index = 0;
+
+	dt_for_each_compatible(dt_root, xscom, "ibm,xscom") {
+		snprintf(namebuf, sizeof(namebuf), "npu@%x", NPU_BASE);
+		npu = dt_new(xscom, namebuf);
+		dt_add_property_cells(npu, "reg", NPU_BASE, NPU_SIZE);
+		dt_add_property_strings(npu, "compatible", "ibm,power9-npu");
+
+		dt_add_property_cells(npu, "ibm,phb-index", phb_index++);
+		dt_add_property_cells(npu, "ibm,npu-index", npu_index++);
+		dt_add_property_cells(npu, "ibm,npu-links", 6);
+
+		create_link(npu, 0, 0);
+		create_link(npu, 0, 1);
+		create_link(npu, 1, 2);
+		create_link(npu, 1, 3);
+		create_link(npu, 2, 4);
+		create_link(npu, 2, 5);
+	}
+}
+
 #define PHB4_SHARED_SLOT_IDX_WITHERSPOON     3
 
 static bool witherspoon_probe(void)
@@ -43,6 +310,11 @@ static bool witherspoon_probe(void)
 	/* Setup UART for use by OPAL (Linux hvc) */
 	uart_set_console_policy(UART_CONSOLE_OPAL);
 
+	/* Add NPU2 bindings */
+	dt_create_npu2();
+
+	slot_table_init(witherspoon_phb_table);
+
 	return true;
 }
 
-- 
2.1.4