[Skiboot] [PATCH 2/6] core/test: make cpu.h usable in tests

[Oliver O'Halloran]

Adds an #ifdef around this_cpu() so that it can be used inside test
code and fakes out the inline assembly used for barrier instructions
and setting the SMT priorities.

Signed-off-by: Oliver O'Halloran <oohall at gmail.com>
---
 include/cpu.h       |  5 +++++
 include/processor.h | 20 ++++++++++++++++++++
 2 files changed, 25 insertions(+)

diff --git a/include/cpu.h b/include/cpu.h
index 2d6969948040..b1e887cceb01 100644
--- a/include/cpu.h
+++ b/include/cpu.h
@@ -193,7 +193,12 @@ extern u8 get_available_nr_cores_in_chip(u32 chip_id);
 		core = next_available_core_in_chip(core, chip_id))
 
 /* Return the caller CPU (only after init_cpu_threads) */
+#ifndef __TEST__
 register struct cpu_thread *__this_cpu asm("r13");
+#else
+static struct cpu_thread fake_cpu;
+static struct cpu_thread *__this_cpu = &fake_cpu;
+#endif
 static inline __nomcount struct cpu_thread *this_cpu(void)
 {
 	return __this_cpu;
diff --git a/include/processor.h b/include/processor.h
index 5906b8657c1b..6f73aacd6872 100644
--- a/include/processor.h
+++ b/include/processor.h
@@ -201,6 +201,8 @@
 
 #else /* __ASSEMBLY__ */
 
+#ifndef __TEST__
+
 #include <compiler.h>
 #include <stdint.h>
 
@@ -320,6 +322,24 @@ static inline void st_le32(uint32_t *addr, uint32_t val)
 	asm volatile("stwbrx %0,0,%1" : : "r"(val), "r"(addr), "m"(*addr));
 }
 
+#else  /* __TEST__ */
+
+#define smt_lowest()
+#define smt_low()
+#define smt_medium()
+#define smt_high()
+#define smt_medium_high()
+#define smt_medium_low()
+#define smt_extra_high()
+#define smt_very_low()
+
+#define eieio()
+#define sync()
+#define lwsync()
+#define isync()
+
+#endif /* __TEST__ */
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* __PROCESSOR_H */
-- 
2.9.3