[Skiboot] [PATCH 3/5] phb4: Mask link down errors during reset

[Russell Currey]

During a hot reset the PCI link will drop, so we need to mask link down
events to prevent unnecessary errors.

Signed-off-by: Russell Currey <ruscur at russell.cc>
---
 hw/phb4.c           | 8 ++++++++
 include/phb4-regs.h | 2 ++
 2 files changed, 10 insertions(+)

diff --git a/hw/phb4.c b/hw/phb4.c
index 3957a051..c0bc634c 100644
--- a/hw/phb4.c
+++ b/hw/phb4.c
@@ -1818,6 +1818,14 @@ static void phb4_prepare_link_change(struct pci_slot *slot, bool is_up)
 		/* Don't block PCI-CFG */
 		p->flags &= ~PHB4_CFG_BLOCKED;
 
+		/* Clear error link enable & error link down kill enable */
+		out_be64(p->regs + PHB_PCIE_MISC_STRAP, 0);
+
+		/* Disable all error status indicators that trigger irqs */
+		out_be64(p->regs + PHB_REGB_ERR_INF_ENABLE, 0);
+		out_be64(p->regs + PHB_REGB_ERR_ERC_ENABLE, 0);
+		out_be64(p->regs + PHB_REGB_ERR_FAT_ENABLE, 0);
+
 		/*
 		 * We might lose the bus numbers during the reset operation
 		 * and we need to restore them. Otherwise, some adapters (e.g.
diff --git a/include/phb4-regs.h b/include/phb4-regs.h
index 92bee88f..1ccef3a0 100644
--- a/include/phb4-regs.h
+++ b/include/phb4-regs.h
@@ -288,6 +288,8 @@
 #define PHB_PCIE_LANE_EQ_CNTL21		0x1AF8
 #define PHB_PCIE_LANE_EQ_CNTL22		0x1B00 /* DD1 only */
 #define PHB_PCIE_LANE_EQ_CNTL23		0x1B08 /* DD1 only */
+#define PHB_PCIE_TRACE_CTRL		0x1B20
+#define PHB_PCIE_MISC_STRAP		0x1B30
 
 #define PHB_REGB_ERR_STATUS		0x1C00
 #define PHB_REGB_ERR1_STATUS		0x1C08
-- 
2.13.1