[Skiboot] [PATCH V2] platform/zz: Acknowledge OCC_LOAD mbox message in ZZ

[Shilpasri G Bhat]

Test results with the patch:

root at zz366p1:~# grep -i occ /sys/firmware/opal/msglog
[  156.119232812,7]   OCC Common Area at 0x2003ff800000 size 8MB
[  156.119254467,7]   OCC Common Area at 0x2003ff800000 size 8MB
[  156.119257388,4] OCC common area is not reserved! Reserving
[    7.048006496,6] OCC: Got OCC Load message, scope=0x2 dbob=0x0 seq=0x1
[   11.270891232,5] irq ffff1 name: psi:occ (7/8)
[   11.270927952,5] irq 1ffff1 name: psi:occ (7/108)
[   11.271290688,6]   0x2003ff800000..2003ffffffff : ibm,occ-common-area
[   15.462487072,7] OCC: Chip 00 Data (00002003fd8e2000) = 0190013c39202000
[   15.462491104,7] OCC: Chip 08 Data (00002003fdce2000) = 0190003c39202000
[   15.462494704,5] OCC: All Chip Rdy after 0 ms
[   15.462542096,7] OCC: CPU pstate state device tree init
[   15.462544768,7] OCC: Data (    2003fd8e2000) =  190013c39202000                0
[   15.462549456,7] OCC: Version 90 Min 60 Nom 57 Max 32 Nr States 29

root at zz366p1:~# cpupower frequency-info
analyzing CPU 0:
  driver: powernv-cpufreq
  CPUs which run at the same hardware frequency: 0 1 2 3
  CPUs which need to have their frequency coordinated by software: 0 1 2 3
  maximum transition latency:  Cannot determine or is not supported.
  hardware limits: 2.00 GHz - 2.47 GHz
  available frequency steps:  2.47 GHz, 2.45 GHz, 2.43 GHz, 2.42 GHz, 2.40 GHz,
2.38 GHz, 2.37 GHz, 2.35 GHz, 2.33 GHz, 2.32 GHz, 2.30 GHz, 2.28 GHz, 2.27 GHz,
2.25 GHz, 2.23 GHz, 2.22 GHz, 2.20 GHz, 2.18 GHz, 2.17 GHz, 2.15 GHz, 2.13 GHz,
2.12 GHz, 2.10 GHz, 2.08 GHz, 2.07 GHz, 2.05 GHz, 2.03 GHz, 2.02 GHz, 2.00 GHz
  available cpufreq governors: conservative ondemand userspace powersave
performance schedutil
  current policy: frequency should be within 2.00 GHz and 2.47 GHz.
                  The governor "ondemand" may decide which speed to use
                  within this range.
  current CPU frequency: 2.02 GHz (asserted by call to hardware)


On 06/08/2017 09:56 AM, Shilpasri G Bhat wrote:
> In P9 FSP box, OCC image is pre-loaded. So do not handle the load
> command and send SUCCESS to FSP on recieving OCC_LOAD mbox message.
> 
> Signed-off-by: Shilpasri G Bhat <shilpa.bhat at linux.vnet.ibm.com>
> ---
> Changes from V1:
> - Send SUCCESS on recieving OCC_LOAD.
> 
>  hw/occ.c               | 17 +++++++++++++++--
>  platforms/ibm-fsp/zz.c |  8 +++++++-
>  2 files changed, 22 insertions(+), 3 deletions(-)
> 
> diff --git a/hw/occ.c b/hw/occ.c
> index 34ef9a7..bc3abc7 100644
> --- a/hw/occ.c
> +++ b/hw/occ.c
> @@ -1082,6 +1082,19 @@ static void occ_do_load(u8 scope, u32 dbob_id __unused, u32 seq_id)
>  	if (err)
>  		return;
> 
> +	if (proc_gen == proc_gen_p9) {
> +		/* OCC is pre-loaded in P9, so send SUCCESS to FSP */
> +		rsp = fsp_mkmsg(FSP_CMD_LOAD_OCC_STAT, 2, 0, seq_id);
> +		if (rsp)
> +			rc = fsp_queue_msg(rsp, fsp_freemsg);
> +		if (rc) {
> +			log_simple_error(&e_info(OPAL_RC_OCC_LOAD),
> +				"OCC: Error %d queueing FSP OCC LOAD STATUS msg", rc);
> +			fsp_freemsg(rsp);
> +		}
> +		return;
> +	}
> +
>  	/*
>  	 * Check if hostservices lid caching is complete. If not, queue
>  	 * the load request.
> @@ -1413,8 +1426,8 @@ void occ_p9_interrupt(uint32_t chip_id)
> 
>  void occ_fsp_init(void)
>  {
> -	/* OCC is P8 only */
> -	if (proc_gen != proc_gen_p8)
> +	/* OCC is  supported in P8 and P9 */
> +	if (proc_gen < proc_gen_p8)
>  		return;
> 
>  	/* If we have an FSP, register for notifications */
> diff --git a/platforms/ibm-fsp/zz.c b/platforms/ibm-fsp/zz.c
> index 89d87b4..c13911f 100644
> --- a/platforms/ibm-fsp/zz.c
> +++ b/platforms/ibm-fsp/zz.c
> @@ -44,10 +44,16 @@ static uint32_t ibm_fsp_occ_timeout(void)
>  	return 60;
>  }
> 
> +static void zz_init(void)
> +{
> +	hservices_init();
> +	ibm_fsp_init();
> +}
> +
>  DECLARE_PLATFORM(zz) = {
>  	.name			= "ZZ",
>  	.probe			= zz_probe,
> -	.init			= ibm_fsp_init,
> +	.init			= zz_init,
>  	.exit			= ibm_fsp_exit,
>  	.cec_power_down		= ibm_fsp_cec_power_down,
>  	.cec_reboot		= ibm_fsp_cec_reboot,
>