[Skiboot] [PATCH v2 08/10] npu2: Adjust content of the NTL BAR

[Reza Arbab]

Reflect the changed NTL BAR layout in POWER9 DD2.

Signed-off-by: Reza Arbab <arbab at linux.vnet.ibm.com>
Cc: Alistair Popple <alistair at popple.id.au>
Cc: Andrew Donnellan <andrew.donnellan at au1.ibm.com>
Cc: Frederic Barrat <fbarrat at linux.vnet.ibm.com>
---
 hw/npu2.c           | 13 ++++++++++---
 include/npu2-regs.h |  6 ++++--
 2 files changed, 14 insertions(+), 5 deletions(-)

diff --git a/hw/npu2.c b/hw/npu2.c
index 3b6f8bf..4a51b10 100644
--- a/hw/npu2.c
+++ b/hw/npu2.c
@@ -198,9 +198,13 @@ static void npu2_read_bar(struct npu2 *p, struct npu2_bar *bar)
 		break;
 	case NPU2_NTL0_BAR:
 	case NPU2_NTL1_BAR:
-		bar->base = GETFIELD(NPU2_NTL_BAR_ADDR, val) << 17;
+		bar->base = GETFIELD(NPU2_NTL_BAR_ADDR, val) << 16;
 		enabled = GETFIELD(NPU2_NTL_BAR_ENABLE, val);
-		bar->size = 0x20000;
+
+		if (is_p9dd1())
+			bar->size = 0x20000;
+		else
+			bar->size = 0x10000 << GETFIELD(NPU2_NTL_BAR_SIZE, val);
 		break;
 	case NPU2_GENID_BAR:
 		bar->base = GETFIELD(NPU2_GENID_BAR_ADDR, val) << 16;
@@ -232,8 +236,11 @@ static void npu2_write_bar(struct npu2 *p,
 		break;
 	case NPU2_NTL0_BAR:
 	case NPU2_NTL1_BAR:
-		val = SETFIELD(NPU2_NTL_BAR_ADDR, 0ul, bar->base >> 17);
+		val = SETFIELD(NPU2_NTL_BAR_ADDR, 0ul, bar->base >> 16);
 		val = SETFIELD(NPU2_NTL_BAR_ENABLE, val, enable);
+
+		if (!is_p9dd1())
+			val = SETFIELD(NPU2_NTL_BAR_SIZE, val, 1);
 		break;
 	case NPU2_GENID_BAR:
 		val = SETFIELD(NPU2_GENID_BAR_ADDR, 0ul, bar->base >> 16);
diff --git a/include/npu2-regs.h b/include/npu2-regs.h
index a10f74f..73b6d62 100644
--- a/include/npu2-regs.h
+++ b/include/npu2-regs.h
@@ -135,8 +135,10 @@ void npu2_write_mask(struct npu2 *p, uint64_t reg, uint64_t val, uint64_t mask);
 #define   NPU2_NTL_BAR_ENABLE			PPC_BIT(0)
 #define   NPU2_NTL_BAR_GROUP			PPC_BITMASK(3,6)
 #define   NPU2_NTL_BAR_CHIP			PPC_BITMASK(7,9)
-#define   NPU2_NTL_BAR_NODE_ADDR		PPC_BITMASK(10,34)
-#define   NPU2_NTL_BAR_ADDR			PPC_BITMASK(3,34)
+#define   NPU2_NTL_BAR_NODE_ADDR		PPC_BITMASK(10,35)
+#define   NPU2_NTL_BAR_ADDR			PPC_BITMASK(3,35)
+#define   NPU2_NTL_BAR_POISON			PPC_BIT(36)
+#define   NPU2_NTL_BAR_SIZE			PPC_BITMASK(39,43)
 #define NPU2_PERF_CFG				0x078
 #define NPU2_INHIBIT_CFG			0x080
 #define NPU2_C_ERR_RPT_MSG0			0x088
-- 
1.8.3.1