[Skiboot] [PATCH 6/9] npu2: Adjust content of the GENID BAR

[Alistair Popple]

On Fri, 14 Jul 2017 10:39:25 AM Reza Arbab wrote:
> Reflect the changed GENID BAR layout in POWER9 DD2.
> 
> Cc: Alistair Popple <alistair at popple.id.au>
> Signed-off-by: Reza Arbab <arbab at linux.vnet.ibm.com>
> ---
>  hw/npu2.c           | 12 ++++++++++--
>  include/npu2-regs.h |  7 +++++--
>  2 files changed, 15 insertions(+), 4 deletions(-)
> 
> diff --git a/hw/npu2.c b/hw/npu2.c
> index e6bb3c3..cba6e3d 100644
> --- a/hw/npu2.c
> +++ b/hw/npu2.c
> @@ -201,7 +201,11 @@ static void npu2_read_bar(struct npu2 *p, struct npu2_bar *bar)
>  		bar->size = 0x20000;
>  		break;
>  	case NPU2_GENID_BAR:
> -		bar->base = GETFIELD(NPU2_GENID_BAR_ADDR, val) << 17;
> +		if (is_p9dd1())

Do we really need this? Didn't DD2 just add an extra bit at the start of the
field that we don't touch on NVLink?

Ie. You are not actually changing the value of the register so I think you could
just do this:

> +			bar->base = GETFIELD(NPU2_GENID_BAR_ADDR, val) << 16;

On both DD1 and DD2.

> +			bar->base = GETFIELD(NPU2_DD1_GENID_BAR_ADDR, val) << 17;
> +		else
> +			bar->base = GETFIELD(NPU2_GENID_BAR_ADDR, val) << 16;
> +
>  		enabled = GETFIELD(NPU2_GENID_BAR_ENABLE, val);
>  		bar->size = 0x20000;
>  		break;
> @@ -234,7 +238,11 @@ static void npu2_write_bar(struct npu2 *p,
>  		val = SETFIELD(NPU2_NTL_BAR_ENABLE, val, enable);
>  		break;
>  	case NPU2_GENID_BAR:
> -		val = SETFIELD(NPU2_GENID_BAR_ADDR, 0ul, bar->base >> 17);
> +		if (is_p9dd1())
> +			val = SETFIELD(NPU2_DD1_GENID_BAR_ADDR, 0ul, bar->base >> 17);
> +		else
> +			val = SETFIELD(NPU2_GENID_BAR_ADDR, 0ul, bar->base >> 16);
> +
>  		val = SETFIELD(NPU2_GENID_BAR_ENABLE, val, enable);
>  		break;
>  	default:
> diff --git a/include/npu2-regs.h b/include/npu2-regs.h
> index fb85729..976adb8 100644
> --- a/include/npu2-regs.h
> +++ b/include/npu2-regs.h
> @@ -122,8 +122,11 @@ void npu2_write_mask(struct npu2 *p, uint64_t reg, uint64_t val, uint64_t mask);
>  #define   NPU2_GENID_BAR_ENABLE			PPC_BIT(0)
>  #define   NPU2_GENID_BAR_GROUP			PPC_BITMASK(3,6)
>  #define   NPU2_GENID_BAR_CHIP			PPC_BITMASK(7,9)
> -#define   NPU2_GENID_BAR_NODE_ADDR		PPC_BITMASK(10,34)
> -#define   NPU2_GENID_BAR_ADDR			PPC_BITMASK(3,34)
> +#define   NPU2_DD1_GENID_BAR_NODE_ADDR		PPC_BITMASK(10,34)
> +#define   NPU2_GENID_BAR_NODE_ADDR		PPC_BITMASK(10,35)
> +#define   NPU2_DD1_GENID_BAR_ADDR		PPC_BITMASK(3,34)
> +#define   NPU2_GENID_BAR_ADDR			PPC_BITMASK(3,35)
> +#define   NPU2_GENID_BAR_POISON			PPC_BIT(39)
>  #define NPU2_LOW_WATER_MARKS			0x040
>  #define NPU2_HIGH_WATER_MARKS			0x048
>  #define NPU2_RELAXED_ORDERING_CFG0		0x050
>