[Skiboot] [PATCH v5 0/7] Enable VAS

Sukadev Bhattiprolu sukadev at linux.vnet.ibm.com
Thu Jan 26 12:32:26 AEDT 2017

Power9 introduces a hardware subsystem referred to as the Virtual
Accelerator Switchboard (VAS). VAS allows kernel subsystems and user
space processes to directly access the Nest Accelerator (NX) engines
which implement compression and encryption algorithms in the hardware.

NX has been in Power processors since Power7+, but access to the NX
engines was through the 'icswx' instruction which is only available
to the kernel/hypervisor. Starting with Power9, access to the NX
engines is provided to both kernel and user space processes through

The switchboard (i.e VAS) multiplexes accesses between "receivers" and
"senders", where the "receivers" are typically the NX engines and
"senders" are the kernel subsystems and user processors that wish to
access the receivers (NX engines).  Once a sender is "connected" to 
a receiver through the switchboard, the sender can submit compression/
encryption requests to the hardware using the new (in PowerISA 3.0)
"copy" and "paste" instructions.

In the initial OPAL and PowerNV kernel patchsets, the "senders" can
only be kernel subsystems (i.e NX-842 driver). A follow-on patch set
will allow senders to be user-space processes.

This OPAL patch set initializes the VAS registers and makes the VAS
hardware available to the NX-842 driver in the kernel. It also provides
some interfaces that the NX-842 subsystem in OPAL needs to initialize
the NX hardware in Power9.

This patchset has been tested in a Simics Power9 environment using:
	- the corresponding VAS kernel patchset [1]
	- modified NX-842 OPAL and kernel drivers, and
	- a compression self-test module from Power8.

A newer version of the VAS kernel patchset, as well as the OPAL and
kernel patchsets for NX-842 driver will be posted separately. All four
are needed to effectively use VAS/NX in Power9.

Thanks to Haren Myneni for the NX-842 modifications and help with
testing, Ben Herrenschmidt, Michael Ellerman and Michael Neuling for
input on working with the hardware and Oliver O'Halloran and Balbir
Singh for review comments.

[1] RFC version of VAS kernel patch set:

	- Create device tree entries for HVWC, UWC and Paste address; drop
	  the vas-#windows entries as number of windows are constant
	- Assign an unique vas-id to each instance and export it in DT.
	- Drop the patch to read FIR. Will include it in a follow-on patchset.

	- Comments from Balbir: Made some functions inline; added some device
	  tree nodes
	- Dropped the patch to allocate/return IRQ ports for now. Will
	  repost the patch later.

       - [Oliver O'Halloran] Fold changes to vas.c and Makefile.inc from
                patch 1 into current patch; use constant 'true' for the
                (unnecessary) macros that were removed by earlier patch;
                free wcbs memory if any chip fails initialization;use
                prolog()/prerror() instead of printf; Use out_be64() to
                write to the MMIO address

       - [Oliver O'Halloran, Alistair Popple] Use proc_gen to check for P9

	- Drop BenH's patch (interface to retrieve IPI trigger port) from
	  this set since it has been merged into skiboot.
	- Minor code reorg to address Alistair Popple's comment (Patch 5).

Sukadev Bhattiprolu (7):
  Define helpers to extract P9 node/chip ids
  vas: Define macros of constants and register fields
  vas: Initialize VAS registers
  vas: Define helper to compute window paste address
  vas: Create device tree node
  vas: Define vas_get_hvwc_mmio_bar interface
  vas: Define vas_get_wcbs_bar interface

 core/Makefile.inc |   2 +-
 core/init.c       |   4 +
 core/vas.c        | 375 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
 include/chip.h    |   7 +
 include/vas.h     | 158 +++++++++++++++++++++++
 5 files changed, 545 insertions(+), 1 deletion(-)
 create mode 100644 core/vas.c
 create mode 100644 include/vas.h


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