[Skiboot] [PATCH 05/13] xive: Set the FORCE_TM_LOCAL bit in CQ_PBI_CTL

[Benjamin Herrenschmidt]

This bits saves the day if the special EX BARs happens to
be misconfigured. There is no drawback to having it always
set so let's do so.

Signed-off-by: Benjamin Herrenschmidt <benh at kernel.crashing.org>
---
 hw/xive.c      | 2 +-
 include/xive.h | 5 +++++
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/hw/xive.c b/hw/xive.c
index 81ff30c..6908835 100644
--- a/hw/xive.c
+++ b/hw/xive.c
@@ -1594,7 +1594,7 @@ static bool xive_config_init(struct xive *x)
 	uint64_t val __unused;
 
 	/* Configure PC and VC page sizes and disable Linux trigger mode */
-	xive_regwx(x, CQ_PBI_CTL, CQ_PBI_PC_64K | CQ_PBI_VC_64K);
+	xive_regwx(x, CQ_PBI_CTL, CQ_PBI_PC_64K | CQ_PBI_VC_64K | CQ_PBI_FORCE_TM_LOCAL);
 	if (x->last_reg_error)
 		return false;
 
diff --git a/include/xive.h b/include/xive.h
index ab5ab80..e9a01c3 100644
--- a/include/xive.h
+++ b/include/xive.h
@@ -64,6 +64,7 @@
 #define  CQ_PBI_PC_64K		PPC_BIT(5)
 #define  CQ_PBI_VC_64K		PPC_BIT(6)
 #define  CQ_PBI_LNX_TRIG	PPC_BIT(7)
+#define  CQ_PBI_FORCE_TM_LOCAL	PPC_BIT(22)
 #define CQ_PBO_CTL		0x108
 #define CQ_AIB_CTL		0x110
 #define X_CQ_RST_CTL		0x23
@@ -296,6 +297,10 @@
  *
  * Then we have all these "special" CI ops at these offset that trigger
  * all sorts of side effects:
+ *
+ * We can OR'in these a cache line index from 0...3 (ie, 0, 0x80, 0x100, 0x180)
+ * to select a specific snooper. 0 is pretty busy so 0x80 or 0x100 is recommended
+ * XXX TODO. add that and find way to tell KVM about it.
  */
 #define TM_SPC_ACK_EBB		0x800	/* Load8 ack EBB to reg*/
 #define TM_SPC_ACK_OS_REG	0x810	/* Load16 ack OS irq to reg */
-- 
2.9.3