[Skiboot] [PATCH 5/5] NX: Describe device-tree changes for P9 NX compression engines

[Sukadev Bhattiprolu]

Haren Myneni [haren at linux.vnet.ibm.com] wrote:
> 
> Describing device-tree entries needed for 842 and gzip compression

nit: s/Describing/Describe/

> engines on P9 NX.
> 
> Signed-off-by: Haren Myneni <haren at us.ibm.com>
> ---
>  doc/device-tree/nx.rst |   35 +++++++++++++++++++++++++++++++----
>  1 files changed, 31 insertions(+), 4 deletions(-)
> 
> diff --git a/doc/device-tree/nx.rst b/doc/device-tree/nx.rst
> index 4c54d4b..e0299f2 100644
> --- a/doc/device-tree/nx.rst
> +++ b/doc/device-tree/nx.rst
> @@ -11,11 +11,12 @@ With unique xscom and nx addresses.  Their compatible node contains
>  "ibm,power-nx".
> 
> 
> -NX 842 Coprocessor
> -------------------
> +NX Compression Coprocessor
> +--------------------------
> 
> -This is the memory compression coprocessor, which uses the IBM proprietary
> -842 compression algorithm and format.  Each nx node contains an 842 engine.
> +This is the memory compression coprocessor. On P7+ and P8, uses the IBM
> +proprietary 842 compression algorithm and format. Each nx node contains an 842
s/nx/NX/?
> +engine.
>  ::
> 
>     ibm,842-coprocessor-type	: CT value common to all 842 coprocessors
> @@ -29,6 +30,32 @@ all 842 coprocessors in the system, the CT value will (should) be the same,
>  while each will have a different CI value.  The driver can use CI 0 to allow
>  the hardware to automatically select which coprocessor instance to use.
> 
> +On P9 or later, this compression coprocessor also supports standard GZIP / ZLIB
> +compression algorithm and format. Virtual Accelerator Swirchboard (VAS) is used
> +to access this coprocessor. VAS writes each request in receive FIFOs (RXFIFO)

nit: s/in receive/to receive/

> +which are either high or normal priority  and these FIFOs are bound to
> +coprocessor types (842 and gzip).
> +
> +VAS distinguishes NX requests for the target engines based on logical
> +partition ID (lpid), process ID (pid) and Thread ID (tid). So to create unique
> +(lpid, pid, tid) combination in the system, chip ID, coprocessor type and
> +priority are assigned to lpid, pid and tid respectively. Each NX node contains
> +high and normal FIFOs for each  842 and GZIP engines.

Can you move this last sentence to just before the "VAS writes each
request"... in the previous para?

> +::
> +  /ibm,nx-842-high		: High priority 842 RxFIFO
> +  /ibm,nx-842-normal		: Normal priority 842 RxFIFO
> +  /ibm,nx-gzip-high		: High priority gzip RxFIFO
> +  /ibm,nx-gzip-normal		: Normal priority gzip RxFIFO
> +
> +Each RxFIFO node contains: ::
> +	rx-fifo-address		: Address represents RxFIFO buffer

nit: s/represents/of the/

> +	lpid			: Chip ID
> +	pid			: Coprocessor type (either 842 or gzip)
> +	tid			: Priority (either high or normal)
> +
> +The driver invokes VAS interface for each coprocessor type (842 and gzip) to

s/The driver/During initialization, the driver/

> +setup RxFIFO with rx_fifo_address, lpid, pid and tid for high and nornmal

s/setup/configure the/

> +priority FIFOs.
> 
>  NX RNG Coprocessor
>  ------------------
> -- 
> 1.7.1
> 
>