[Skiboot] [PATCH 1/2] pci: Add a framework for quirks

Gavin Shan gwshan at linux.vnet.ibm.com
Mon Feb 20 11:04:14 AEDT 2017

On Mon, Feb 20, 2017 at 10:12:20AM +1100, Benjamin Herrenschmidt wrote:
>On Mon, 2017-02-20 at 10:04 +1100, Gavin Shan wrote:
>> Also, the memory BAR of one specific PCI device isn't populted. It
>> means we can't fixup the registers in memory BAR and have to do that
>> in kernel. With this patch applied, we're going to have some fixups
>> in skiboot and others in kernel. It's prone to be out of sychronization
>> between skiboot and kernel. So it's possible to do the quirks in kernel
>> only?
>No. The whole point of that specific quirk is that the kernel cannot
>access the relevant information. It's not obtained via the device BARs,
>but via some backdoor into the BMC address space that we want to close.

Ok. Thanks for the explanation. It's reasonable to apply the quirk in
skiboot then. the back-door is LPC to AHB bridge? In PATCH[2/2],
ast_ahb_readl() is used to check SoC revision from some SCU register.


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