[Skiboot] [PATCH v5 0/8] skiboot: OPAL support for IMC instrumentation

Hemant Kumar hemant at linux.vnet.ibm.com
Wed Feb 8 08:11:45 AEDT 2017

Patchset adds support for In Memory Collection instrumentation (IMC)
services in OPAL for Power9. The entire IMC infrastructure consists of
two kinds of Performance Monitoring Units (PMUs) : nest imc pmus (chip
level) and core imc pmus (core level).

Nest IMC PMUs are off core but on chip. And these can be accessed via
in-band scoms. Programming these counters and accumulating the counter
data to memory is done via microcode running in one of the OCC Engines.

Core IMC PMUs handle the per-core counters. These are initialized with
per-core PDBARs, HTM_MODE and EVENT_MASK scoms.

This patchset is to add nest and core IMC instrumentation support in the
OPAL side.

"IMA_CATALOG" partition in PNOR contains multiple device tree binaries
(DTB) in a compressed form with PVR tag. So, when loading the IMA_CATALOG
partition, OPAL passes the system PVR as a "subid" to the load_resource
API. If a catalog dtb is found for a given pvr, it is decompressed and
linked to the main device tree. 

Commit which adds the "IMA_CATALOG" partition to PNOR is :

The root node of a IMC catalog device tree contains nodes for the IMC
PMUs and the common events across the PMUs. Here is an excerpt from
the device tree :
/ {
        name = "";
        compatible = "ibm,opal-in-memory-counters";
        #address-cells = <0x1>;
        #size-cells = <0x1>;
        imc-nest-offset = <0x320000>;
        imc-nest-size = <0x30000>;
        version-id = "";
        NEST_MCS: nest-mcs-events {
                #address-cells = <0x1>;
                #size-cells = <0x1>;
                event at 0 {
                        event-name = "RRTO_QFULL_NO_DISP" ;
                        reg = <0x0 0x8>;
                        desc = "RRTO not dispatched in MCS0 due to capacity - pulses once for each time a valid RRTO op is not dispatched due to a command list full condition" ;
                event at 8 {
                        event-name = "WRTO_QFULL_NO_DISP" ;
                        reg = <0x8 0x8>;
                        desc = "WRTO not dispatched in MCS0 due to capacity - pulses once for each time a valid WRTO op is not dispatched due to a command list full condition" ;
        mcs0 {
                compatible = "ibm,imc-counters-nest";
                events-prefix = "PM_MCS0_";
                unit = "";
                scale = "";
                reg = <0x118 0x8>;
                events = < &NEST_MCS >;
        mcs1 {
                compatible = "ibm,imc-counters-nest";
                events-prefix = "PM_MCS1_";
                unit = "";
                scale = "";
                reg = <0x198 0x8>;
                events = < &NEST_MCS >;

	CORE_EVENTS: core-events {
                #address-cells = <0x1>;
                #size-cells = <0x1>;
                event at e0 {
                        event-name = "0THRD_NON_IDLE_PCYC" ;
                        reg = <0xe0 0x8>;
                        desc = "The number of processor cycles when all threads are idle" ;
                event at 120 {
                        event-name = "1THRD_NON_IDLE_PCYC" ;
                        reg = <0x120 0x8>;
                        desc = "The number of processor cycles when exactly one SMT thread is executing non-idle code" ;
        core {
                compatible = "ibm,imc-counters-core";
                events-prefix = "CPM_";
                unit = "";
                scale = "";
                reg = <0x0 0x8>;
                events = < &CORE_EVENTS >;
        thread {
                compatible = "ibm,imc-counters-core";
                events-prefix = "CPM_";
                unit = "";
                scale = "";
                reg = <0x0 0x8>;
                events = < &CORE_EVENTS >;

For any IMC PMU node (mcs0, mcs1, mcs2, core, thread etc), its events
property points to the events node which gives us the event
information for that PMU.
For e.g., let's take the mcs0 PMU node from the above excerpt, "events"
property points us to the events list for this PMU and "events-prefix"
property helps us to create the correct event name for this PMU. So,
"RRTO_QFULL_NO_DISP" event name from "nest-mcs-events" becomes
This new design of the DTS file saves up a lot of space for the device
tree, since a lot of event names are common accross PMUs. For core and
thread IMC PMUs, all the event names are common.

Each event in the device tree contains "event-name" and "offset".
Some of the PMUs may contain properties such as "scale" and "unit" which
reflects the fact that all the events inside this PMU will have the
same "scale" and "unit" values.

Why this design for the IMC DTS files?
The DTS files for Power 9 contain the IMC PMUs for nest, core and thread
IMC PMUs. There could be an argument to design the device tree
in such a way, so that one can use of_translate_address() directly on
the event nodes and can get the cpu address for that event. However,
there are some issues with that.
For nest imc, we need to attach the device tree to per-chip HOMER region
node. For multiple chips, this will increase replication.
For core imc, we allocate the memory in the kernel for each core and the
base location for core imc is not fixed. Hence, we can't use
of_translate_address on the core events.
For thread imc, we allocate memory for each linux process which needs to
be monitored. This will be particularly difficult to take care of in
the device tree since, the allocation will be dynamic.

So, from the OPAL side, we need to :
 - Find out the current processor's PVR.
 - Fetch the "IMA_CATALOG" partition.
 - Fetch the correct subpartition based on the current processor's PVR.
 - Decompress the blob taken from the subpartition.
 - Expand the (now uncompressed) device tree binary and attach it to the
   system's device tree, so that, it can now be discovered by the
 - Look at the IMC availability vector which denotes which of the nest
   PMUs are available and remove the unavailable PMU nodes from the
   device tree.

Note that :
 - We are working with the catalog team to make the new design for the
   DTS files upstream.
 - The commit which adds the IMA_CATALOG partition to PNOR is mentioned
 - Since OPAL lacks a xz decompression library, an xz decompression
   library has been reused from the hostboot repo (link has been
   mentioned in patch 3/7).
 - The last patch in the series is to add "chip-id" to reserved homer
   region node in the device tree. This will give us the homer region's
   associated chip in the kernel (which will be needed to fetch the
   counter values from the required chip).

This Patchset does 3 things :

1) At the time of boot, it detects the IMA_CATALOG resource. Based on
   the current processor's PVR value, it fetches the appropriate
   subpartition. The blob in this subpartition is then uncompressed and the
   flattened device tree is obtained. This dtb is then expanded and then
   linked to the system's device tree under
   "/proc/device-tree/ima-counters". The node "ima-counters" is a new node
   created in this patchset. The kernel can then discover this node based
   on its compatibility field.

2) It implements an opal call to control a microcode running in one of the
   OCC engines (responsible for nest IMC data collection) from kernel to
   start/stop Nest PMU counter data collection.

3) It also implements an opal call to control the core IMC engine for each
   core to initialize, enable and disable the counters as specified the
   host kernel.

This patchset is based on the initial work for Nest Instrumentation done
by Madhavan Srinivasan, which can be found here :

Changelog :
 v4 -> v5:
 - Changed the cover letter to show the new IMC DTS format (which removes
 - No visible changes in the code.
 v3 -> v4:
 Major Changes include :
 - Patchset now has support for core level IMC PMUs support.

 v2 -> v3 :
 Major changes include
 - Addressed review comments from Oliver O'Halloran.
 - Renamed this infrastructure from IMA (In-Memory Accumulation) to IMC
   (In-Memory Collection), since, the name IMA conflicts with existing
   IMA (Integrity Measurement Architecture) in the linux kernel.
 - Patches 2 and 4 have been merged together (3/6).
 - Patch 3 (xz library) has been moved to Patch 2/6.

Changes since v1 have been mentioned in the individual patches.

Hemant Kumar (7):
  skiboot: Nest IMC macro definitions
  skiboot: Add a library for xz
  skiboot: Find the IMC DTB
  skiboot: Add opal call to enable/disable Nest IMC microcode
  skiboot: Add core IMC related counter configuration OPAL call
  skiboot: Add documentation for nest IMC opal call
  skiboot: Add documentation for the Core IMC opal call

Vasant Hegde (1):
  skiboot: Add chip id to HOMER reserved region

 Makefile.main                           |    5 +-
 core/flash.c                            |    1 +
 core/init.c                             |    7 +
 doc/opal-api/opal-core-imc-counters.rst |   40 ++
 doc/opal-api/opal-nest-imc-counters.rst |   49 ++
 hw/Makefile.inc                         |    2 +-
 hw/homer.c                              |   30 +
 hw/imc.c                                |  393 ++++++++++
 include/imc.h                           |  127 ++++
 include/nest_imc.h                      |   85 +++
 include/opal-api.h                      |   17 +-
 include/platform.h                      |    1 +
 include/skiboot.h                       |    1 +
 libxz/Makefile.inc                      |    7 +
 libxz/xz.h                              |  312 ++++++++
 libxz/xz_config.h                       |  133 ++++
 libxz/xz_crc32.c                        |   67 ++
 libxz/xz_dec_lzma2.c                    | 1183 +++++++++++++++++++++++++++++++
 libxz/xz_dec_stream.c                   |  855 ++++++++++++++++++++++
 libxz/xz_lzma2.h                        |  212 ++++++
 libxz/xz_private.h                      |  164 +++++
 libxz/xz_stream.h                       |   70 ++
 22 files changed, 3757 insertions(+), 4 deletions(-)
 create mode 100644 doc/opal-api/opal-core-imc-counters.rst
 create mode 100644 doc/opal-api/opal-nest-imc-counters.rst
 create mode 100644 hw/imc.c
 create mode 100644 include/imc.h
 create mode 100644 include/nest_imc.h
 create mode 100644 libxz/Makefile.inc
 create mode 100644 libxz/xz.h
 create mode 100644 libxz/xz_config.h
 create mode 100644 libxz/xz_crc32.c
 create mode 100644 libxz/xz_dec_lzma2.c
 create mode 100644 libxz/xz_dec_stream.c
 create mode 100644 libxz/xz_lzma2.h
 create mode 100644 libxz/xz_private.h
 create mode 100644 libxz/xz_stream.h


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