[Skiboot] [PATCH 3/5] xive/psi/lpc: Handle proper clearing of LPC SerIRQ latch on DD1

[Stewart Smith]

Benjamin Herrenschmidt <benh at kernel.crashing.org> writes:
> On DD1, the LPC SerIRQ are latched to 1 in HW but never back to 0,
> we need an explicit clear after running the handler. (Not before
> as they are level interrupts, they will be latched again if they
> are still pending).
>
> For now we do that in lpc_dispatch_ser_irqs() but that only works
> for interrupts routed to OPAL.
>
> In order to support routing LPC interrutps to Linux, we need a custom
> EOI handler that does the clearing of the latch before we do the
> EOI in the ESB.
>
> Signed-off-by: Benjamin Herrenschmidt <benh at kernel.crashing.org>

Merged to master as of 7d252cdeb5f5f85d4a386859e0c87613162bcf31

-- 
Stewart Smith
OPAL Architect, IBM.