[Skiboot] [PATCH 1/9] npu2: Split out common helper functions into separate file

Andrew Donnellan andrew.donnellan at au1.ibm.com
Tue Dec 19 17:17:46 AEDT 2017


On 19/12/17 11:37, Alistair Popple wrote:
>> +bool is_p9dd1(void)
> 
> Does OpenCAPI still need this? If not we should just drop it and DD1 support
> along with it as it's very unlikely anything still works there.

OpenCAPI has no DD1 support whatsoever. If you want to drop DD1 support 
for NVLink then I have no objections!


Andrew

> 
> - Alistair
> 
>> +{
>> +	struct proc_chip *chip = next_chip(NULL);
>> +
>> +	return chip &&
>> +	       (chip->type == PROC_CHIP_P9_NIMBUS ||
>> +		chip->type == PROC_CHIP_P9_CUMULUS) &&
>> +	       (chip->ec_level & 0xf0) == 0x10;
>> +}
>> +
>> +/*
>> + * We use the indirect method because it uses the same addresses as
>> + * the MMIO offsets (NPU RING)
>> + */
>> +static void npu2_scom_set_addr(uint64_t gcid, uint64_t scom_base,
>> +			       uint64_t addr, uint64_t size)
>> +{
>> +	uint64_t isa = is_p9dd1() ? NPU2_DD1_MISC_SCOM_IND_SCOM_ADDR :
>> +				    NPU2_MISC_SCOM_IND_SCOM_ADDR;
>> +
>> +	addr = SETFIELD(NPU2_MISC_DA_ADDR, 0ull, addr);
>> +	addr = SETFIELD(NPU2_MISC_DA_LEN, addr, size);
>> +	xscom_write(gcid, scom_base + isa, addr);
>> +}
>> +
>> +void npu2_scom_write(uint64_t gcid, uint64_t scom_base,
>> +		     uint64_t reg, uint64_t size,
>> +		     uint64_t val)
>> +{
>> +	uint64_t isd = is_p9dd1() ? NPU2_DD1_MISC_SCOM_IND_SCOM_DATA :
>> +				    NPU2_MISC_SCOM_IND_SCOM_DATA;
>> +
>> +	npu2_scom_set_addr(gcid, scom_base, reg, size);
>> +	xscom_write(gcid, scom_base + isd, val);
>> +}
>> +
>> +uint64_t npu2_scom_read(uint64_t gcid, uint64_t scom_base,
>> +			uint64_t reg, uint64_t size)
>> +{
>> +	uint64_t val;
>> +	uint64_t isd = is_p9dd1() ? NPU2_DD1_MISC_SCOM_IND_SCOM_DATA :
>> +				    NPU2_MISC_SCOM_IND_SCOM_DATA;
>> +
>> +	npu2_scom_set_addr(gcid, scom_base, reg, size);
>> +	xscom_read(gcid, scom_base + isd, &val);
>> +
>> +	return val;
>> +}
>> +
>> +void npu2_write_4b(struct npu2 *p, uint64_t reg, uint32_t val)
>> +{
>> +	npu2_scom_write(p->chip_id, p->xscom_base, reg, NPU2_MISC_DA_LEN_4B,
>> +			(uint64_t)val << 32);
>> +}
>> +
>> +uint32_t npu2_read_4b(struct npu2 *p, uint64_t reg)
>> +{
>> +	return npu2_scom_read(p->chip_id, p->xscom_base, reg,
>> +			      NPU2_MISC_DA_LEN_4B) >> 32;
>> +}
>> +
>> +void npu2_write(struct npu2 *p, uint64_t reg, uint64_t val)
>> +{
>> +	npu2_scom_write(p->chip_id, p->xscom_base, reg, NPU2_MISC_DA_LEN_8B, val);
>> +}
>> +
>> +uint64_t npu2_read(struct npu2 *p, uint64_t reg)
>> +{
>> +	return npu2_scom_read(p->chip_id, p->xscom_base, reg, NPU2_MISC_DA_LEN_8B);
>> +}
>> +
>> +void npu2_write_mask(struct npu2 *p, uint64_t reg, uint64_t val, uint64_t mask)
>> +{
>> +	uint64_t new_val;
>> +
>> +	new_val = npu2_read(p, reg);
>> +	new_val &= ~mask;
>> +	new_val |= val & mask;
>> +	npu2_scom_write(p->chip_id, p->xscom_base, reg, NPU2_MISC_DA_LEN_8B, new_val);
>> +}
>> +
>> +void npu2_write_mask_4b(struct npu2 *p, uint64_t reg, uint32_t val, uint32_t mask)
>> +{
>> +	uint32_t new_val;
>> +
>> +	new_val = npu2_read_4b(p, reg);
>> +	new_val &= ~mask;
>> +	new_val |= val & mask;
>> +	npu2_scom_write(p->chip_id, p->xscom_base, reg, NPU2_MISC_DA_LEN_4B,
>> +			(uint64_t)new_val << 32);
>> +}
>> diff --git a/hw/npu2.c b/hw/npu2.c
>> index 7ffb094..e66ceb9 100644
>> --- a/hw/npu2.c
>> +++ b/hw/npu2.c
>> @@ -64,98 +64,6 @@
>>    * configure one particular BAR.
>>    */
>>   
>> -static bool is_p9dd1(void)
>> -{
>> -	struct proc_chip *chip = next_chip(NULL);
>> -
>> -	return chip &&
>> -	       (chip->type == PROC_CHIP_P9_NIMBUS ||
>> -		chip->type == PROC_CHIP_P9_CUMULUS) &&
>> -	       (chip->ec_level & 0xf0) == 0x10;
>> -}
>> -
>> -/*
>> - * We use the indirect method because it uses the same addresses as
>> - * the MMIO offsets (NPU RING)
>> - */
>> -static void npu2_scom_set_addr(uint64_t gcid, uint64_t scom_base,
>> -			       uint64_t addr, uint64_t size)
>> -{
>> -	uint64_t isa = is_p9dd1() ? NPU2_DD1_MISC_SCOM_IND_SCOM_ADDR :
>> -				    NPU2_MISC_SCOM_IND_SCOM_ADDR;
>> -
>> -	addr = SETFIELD(NPU2_MISC_DA_ADDR, 0ull, addr);
>> -	addr = SETFIELD(NPU2_MISC_DA_LEN, addr, size);
>> -	xscom_write(gcid, scom_base + isa, addr);
>> -}
>> -
>> -static void npu2_scom_write(uint64_t gcid, uint64_t scom_base,
>> -			    uint64_t reg, uint64_t size,
>> -			    uint64_t val)
>> -{
>> -	uint64_t isd = is_p9dd1() ? NPU2_DD1_MISC_SCOM_IND_SCOM_DATA :
>> -				    NPU2_MISC_SCOM_IND_SCOM_DATA;
>> -
>> -	npu2_scom_set_addr(gcid, scom_base, reg, size);
>> -	xscom_write(gcid, scom_base + isd, val);
>> -}
>> -
>> -static uint64_t npu2_scom_read(uint64_t gcid, uint64_t scom_base,
>> -			       uint64_t reg, uint64_t size)
>> -{
>> -	uint64_t val;
>> -	uint64_t isd = is_p9dd1() ? NPU2_DD1_MISC_SCOM_IND_SCOM_DATA :
>> -				    NPU2_MISC_SCOM_IND_SCOM_DATA;
>> -
>> -	npu2_scom_set_addr(gcid, scom_base, reg, size);
>> -	xscom_read(gcid, scom_base + isd, &val);
>> -
>> -	return val;
>> -}
>> -
>> -void npu2_write_4b(struct npu2 *p, uint64_t reg, uint32_t val)
>> -{
>> -	npu2_scom_write(p->chip_id, p->xscom_base, reg, NPU2_MISC_DA_LEN_4B,
>> -			(uint64_t)val << 32);
>> -}
>> -
>> -uint32_t npu2_read_4b(struct npu2 *p, uint64_t reg)
>> -{
>> -	return npu2_scom_read(p->chip_id, p->xscom_base, reg,
>> -			      NPU2_MISC_DA_LEN_4B) >> 32;
>> -}
>> -
>> -void npu2_write(struct npu2 *p, uint64_t reg, uint64_t val)
>> -{
>> -	npu2_scom_write(p->chip_id, p->xscom_base, reg, NPU2_MISC_DA_LEN_8B, val);
>> -}
>> -
>> -uint64_t npu2_read(struct npu2 *p, uint64_t reg)
>> -{
>> -	return npu2_scom_read(p->chip_id, p->xscom_base, reg, NPU2_MISC_DA_LEN_8B);
>> -}
>> -
>> -void npu2_write_mask(struct npu2 *p, uint64_t reg, uint64_t val, uint64_t mask)
>> -{
>> -	uint64_t new_val;
>> -
>> -	new_val = npu2_read(p, reg);
>> -	new_val &= ~mask;
>> -	new_val |= val & mask;
>> -	npu2_scom_write(p->chip_id, p->xscom_base, reg, NPU2_MISC_DA_LEN_8B, new_val);
>> -}
>> -
>> -void npu2_write_mask_4b(struct npu2 *p, uint64_t reg, uint32_t val, uint32_t mask)
>> -{
>> -	uint32_t new_val;
>> -
>> -	new_val = npu2_read_4b(p, reg);
>> -	new_val &= ~mask;
>> -	new_val |= val & mask;
>> -	npu2_scom_write(p->chip_id, p->xscom_base, reg, NPU2_MISC_DA_LEN_4B,
>> -			(uint64_t)new_val << 32);
>> -}
>> -
>>   /* Set a specific flag in the vendor config space */
>>   void npu2_set_link_flag(struct npu2_dev *ndev, uint8_t flag)
>>   {
>> diff --git a/include/npu2-regs.h b/include/npu2-regs.h
>> index fdaad19..cf74431 100644
>> --- a/include/npu2-regs.h
>> +++ b/include/npu2-regs.h
>> @@ -23,6 +23,11 @@ void npu2_write4(struct npu2 *p, uint64_t reg, uint64_t val);
>>   uint64_t npu2_read(struct npu2 *p, uint64_t reg);
>>   void npu2_write(struct npu2 *p, uint64_t reg, uint64_t val);
>>   void npu2_write_mask(struct npu2 *p, uint64_t reg, uint64_t val, uint64_t mask);
>> +uint64_t npu2_scom_read(uint64_t gcid, uint64_t scom_base,
>> +			uint64_t reg, uint64_t size);
>> +void npu2_scom_write(uint64_t gcid, uint64_t scom_base,
>> +		     uint64_t reg, uint64_t size,
>> +		     uint64_t val);
>>   
>>   /* These aren't really NPU specific registers but we initialise them in NPU
>>    * code */
>> diff --git a/include/npu2.h b/include/npu2.h
>> index dae152a..d0c9ac5 100644
>> --- a/include/npu2.h
>> +++ b/include/npu2.h
>> @@ -163,4 +163,6 @@ void npu2_dev_procedure_reset(struct npu2_dev *dev);
>>   void npu2_set_link_flag(struct npu2_dev *ndev, uint8_t flag);
>>   void npu2_clear_link_flag(struct npu2_dev *ndev, uint8_t flag);
>>   extern int nv_zcal_nominal;
>> +bool is_p9dd1(void);
>> +
>>   #endif /* __NPU2_H */
>>
> 
> 

-- 
Andrew Donnellan              OzLabs, ADL Canberra
andrew.donnellan at au1.ibm.com  IBM Australia Limited



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