[Skiboot] [PATCH v2 5/5] xive: Ensure VC informational FIRs are masked

[Benjamin Herrenschmidt]

Some HostBoot versions leave those as checkstop, they are harmless
and can sometimes occur during normal operations.

Signed-off-by: Benjamin Herrenschmidt <benh at kernel.crashing.org>
Tested-by: Oliver O'Halloran <oohall at gmail.com>
---
 hw/xive.c      | 5 +++++
 include/xive.h | 6 ++++++
 2 files changed, 11 insertions(+)

diff --git a/hw/xive.c b/hw/xive.c
index bab4892f..04dceda6 100644
--- a/hw/xive.c
+++ b/hw/xive.c
@@ -1780,6 +1780,11 @@ static bool xive_config_init(struct xive *x)
 	val |= VC_EQC_CONF_ENABLE_END_u_BIT;
 	xive_regw(x, VC_EQC_CONFIG, val);
 
+	/* Disable error reporting in the FIR for info errors
+	 * from the VC.
+	 */
+	xive_regw(x, CQ_FIRMASK_OR, 3ull);
+
 	return true;
 }
 
diff --git a/include/xive.h b/include/xive.h
index 22e6a895..824ca0b8 100644
--- a/include/xive.h
+++ b/include/xive.h
@@ -70,6 +70,12 @@
 #define CQ_AIB_CTL		0x110
 #define X_CQ_RST_CTL		0x23
 #define CQ_RST_CTL		0x118
+#define X_CQ_FIRMASK		0x33
+#define CQ_FIRMASK		0x198
+#define X_CQ_FIRMASK_AND	0x34
+#define CQ_FIRMASK_AND		0x1a0
+#define X_CQ_FIRMASK_OR		0x35
+#define CQ_FIRMASK_OR		0x1a8
 
 /* PC LBS1 register offsets */
 #define X_PC_TCTXT_CFG		0x100
-- 
2.14.3