[Skiboot] [PATCH 6/6] xive: Ensure VC informational FIRs are masked
Oliver
oohall at gmail.com
Thu Dec 7 12:55:16 AEDT 2017
On Thu, Dec 7, 2017 at 4:39 AM, Benjamin Herrenschmidt
<benh at kernel.crashing.org> wrote:
> Some HostBoot versions leave those as checkstop, they are harmless
> and can sometimes occur during normal operations.
>
> Signed-off-by: Benjamin Herrenschmidt <benh at kernel.crashing.org>
> ---
> hw/xive.c | 5 +++++
> include/xive.h | 6 ++++++
> 2 files changed, 11 insertions(+)
>
> diff --git a/hw/xive.c b/hw/xive.c
> index b08c6783..184564f4 100644
> --- a/hw/xive.c
> +++ b/hw/xive.c
> @@ -1776,6 +1776,11 @@ static bool xive_config_init(struct xive *x)
> val |= VC_EQC_CONF_ENABLE_END_u_BIT;
> xive_regw(x, VC_EQC_CONFIG, val);
>
> + /* Disable error reporting in the FIR for info errors
> + * from the VC.
> + */
> + xive_regw(x, CQ_FIRMASK_OR, 3ull);
Should we be masking the PC INFO fir bits too?
> +
> return true;
> }
>
> diff --git a/include/xive.h b/include/xive.h
> index 22e6a895..824ca0b8 100644
> --- a/include/xive.h
> +++ b/include/xive.h
> @@ -70,6 +70,12 @@
> #define CQ_AIB_CTL 0x110
> #define X_CQ_RST_CTL 0x23
> #define CQ_RST_CTL 0x118
> +#define X_CQ_FIRMASK 0x33
> +#define CQ_FIRMASK 0x198
> +#define X_CQ_FIRMASK_AND 0x34
> +#define CQ_FIRMASK_AND 0x1a0
> +#define X_CQ_FIRMASK_OR 0x35
> +#define CQ_FIRMASK_OR 0x1a8
>
> /* PC LBS1 register offsets */
> #define X_PC_TCTXT_CFG 0x100
> --
> 2.14.3
>
> _______________________________________________
> Skiboot mailing list
> Skiboot at lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/skiboot
It might be worth checking with the PRD team to see if they want to
log the information errors rather than just masking them.
Tested-by: Oliver O'Halloran <oohall at gmail.com>
More information about the Skiboot
mailing list