[Skiboot] [PATCH 06/16] core/pci: Fix PCIe slot power state

Stewart Smith stewart at linux.vnet.ibm.com
Tue Sep 27 17:32:52 AEST 2016

Gavin Shan <gwshan at linux.vnet.ibm.com> writes:
> The power state of PCIe slot should be retrieved from the PCIe
> Slot Control register (offset: +0x18), instead of having the
> fixed state (power-off) wrongly. Otherwise, we have mismatched
> states (off in software, on in hardware) after powering off the
> slot.
> This retrieves the PCIe slot power state from PCIe Slot Control
> Register if the power control is supported. Otherwise, the initial
> power state of the PCIe slot doesn't matter and it's set to on.
> Signed-off-by: Gavin Shan <gwshan at linux.vnet.ibm.com>
> ---
>  core/pcie-slot.c | 15 ++++++++++++++-
>  1 file changed, 14 insertions(+), 1 deletion(-)

Should this also be CC: stable ?
Perhaps also Fixes: bc66fb67aee6f9e6520120c2476d58f3899c9221 ?

Stewart Smith
OPAL Architect, IBM.

More information about the Skiboot mailing list