[Skiboot] [PATCH 16/16] hw/phb3: Disable ECRC on Broadcom adapter behind PMC switch

[Gavin Shan]

The ECRC generation and check can't be enabled on Broadcom's NIC
(vdid: 14e4:168a) when it seats behind PMC PCIe switch downstream
port (vdid: 11f8:8546). Otherwise, the NIC's config space can't
be accessed and returns 0xFF's on read because of EEH error even
after the EEH error is cleared. The issue is found on Firestone.

  0001:06:00.0 Ethernet controller: Broadcom Corporation \
               NetXtreme II BCM57800 10 Gigabit Ethernet (rev 10)

This disables ECRC generation and check on Broadcom's NIC when it
seats behind PMC PCIe switch downstream port.

Reported-by: Li Meng <shlimeng at cn.ibm.com>
Signed-off-by: Gavin Shan <gwshan at linux.vnet.ibm.com>
---
 hw/phb3.c | 23 +++++++++++++++++++++--
 1 file changed, 21 insertions(+), 2 deletions(-)

diff --git a/hw/phb3.c b/hw/phb3.c
index 050c69b..2d198ac 100644
--- a/hw/phb3.c
+++ b/hw/phb3.c
@@ -436,6 +436,21 @@ static void phb3_switch_port_init(struct phb *phb,
 	pci_cfg_write32(phb, bdfn, aercap + PCIECAP_AER_CAPCTL, val32);
 }
 
+static inline bool phb3_endpoint_report_ecrc(struct pci_device *pd)
+{
+	/* No ECRC generation and check on Broadcom ethernet adapter
+	 * when it seats behind a PMC's PCIe switch downstream port.
+	 * Otherwise, the Broadcom ethernet adapter's config space
+	 * can't be accessed because of frozen PE error even after
+	 * the frozen PE error is cleared.
+	 */
+	if (pd && pd->vdid == 0x168a14e4 &&
+	    pd->parent && pd->parent->vdid == 0x854611f8)
+		return false;
+
+	return true;
+}
+
 static void phb3_endpoint_init(struct phb *phb,
 			       struct pci_device *dev,
 			       int ecap, int aercap)
@@ -473,8 +488,12 @@ static void phb3_endpoint_init(struct phb *phb,
 
 	/* Enable ECRC generation and check */
 	pci_cfg_read32(phb, bdfn, aercap + PCIECAP_AER_CAPCTL, &val32);
-	val32 |= (PCIECAP_AER_CAPCTL_ECRCG_EN |
-		  PCIECAP_AER_CAPCTL_ECRCC_EN);
+	if (phb3_endpoint_report_ecrc(dev))
+		val32 |= (PCIECAP_AER_CAPCTL_ECRCG_EN |
+			  PCIECAP_AER_CAPCTL_ECRCC_EN);
+	else
+		val32 &= ~(PCIECAP_AER_CAPCTL_ECRCG_EN |
+			   PCIECAP_AER_CAPCTL_ECRCC_EN);
 	pci_cfg_write32(phb, bdfn, aercap + PCIECAP_AER_CAPCTL, val32);
 }
 
-- 
2.1.0