[Skiboot] [RFC PATCH 1/7] skiboot: Nest IMA macro definitions

[Hemant Kumar]

Add the macros needed for Nest IMA (In Memory Accumulation)
instrumentation support by creating a new file in include/ called
"ima.h". These macros are needed to discover the catalog subpartition,
enable and disable the nest IMA instrumentation.

Signed-off-by: Hemant Kumar <hemant at linux.vnet.ibm.com>
---
 include/ima.h | 89 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 89 insertions(+)
 create mode 100644 include/ima.h

diff --git a/include/ima.h b/include/ima.h
new file mode 100644
index 0000000..3bde4f3
--- /dev/null
+++ b/include/ima.h
@@ -0,0 +1,89 @@
+/* Copyright 2016 IBM Corp.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *	http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ * implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * IMA (In Memory Accumulation) Instrumentation :
+ * Power9 has IMA instrumentation support with which several metrics of
+ * the platform can be monitored. These metrics are backed by the IMA
+ * Performance Monitoring Units and their counters. They are named as IMA
+ * counters, as the counter data from these counters are fed directly
+ * into a pre-defined memory location.
+ *
+ * Depending on their location and monitoring engines, they are classified
+ * into three domains :
+ * Nest IMA, core IMA and thread IMA.
+ *
+ * Nest counters are per-chip counters and can help in providing utilisation
+ * metrics like memory bandwidth, Xlink/Alink bandwidth etc.
+ *
+ * A microcode in OCC programs the nest counters and moves counter values to
+ * per chip HOMER region in a fixed offset for each unit. Engine has a
+ * control block structure for communication with Hyperviosr(Host OS).
+ */
+
+#ifndef __IMA_H
+#define __IMA_H
+
+/*
+ * Control Block structure offset in HOMER IMA Region
+ */
+#define CB_STRUCT_OFFSET	0x39FC00
+#define CB_STRUCT_CMD		0x39FC08
+#define CB_STRUCT_SPEED		0x39FC10
+#define SLW_IMA_PAUSE		0x2
+#define SLW_IMA_RESUME		0x1
+#define SLW_IMA_NOP		0
+
+/*
+ * Control Block Structure:
+ *
+ * Name          Producer        Consumer        Values  Desc
+ * IMARunStatus   IMA Code       Hypervisor      0       Initializing
+ *                               (Host OS)       1       Running
+ *                                               2       Paused
+ *
+ * IMACommand     Hypervisor     IMA Code        0       NOP
+ *                                               1       Resume
+ *                                               2       Pause
+ *                                               3       Clear and Restart
+ *
+ * IMACollection Hypervisor      IMA Code        0       128us
+ * Speed					 1       256us
+ *                                               2       1ms
+ *                                               3       4ms
+ *                                               4       16ms
+ *                                               5       64ms
+ *                                               6       256ms
+ *                                               7       1000ms
+ */
+struct ima_chip_cb
+{
+        u64 ima_chip_run_status;
+        u64 ima_chip_command;
+        u64 ima_chip_collection_speed;
+};
+
+/* Size of IMA dtb LID (256KBytes) */
+#define IMA_DTB_SIZE		0x40000
+
+/*
+ * Nest IMA operations
+ */
+#define NEST_IMA_PRODUCTION_MODE	0x1
+#define NEST_IMA_ENABLE			0x1
+#define NEST_IMA_DISABLE		0x2
+
+#endif /* __IMA_H */
-- 
2.7.4