[Skiboot] [PATCH] psi: fix the xive registers initialization on P8

[Cédric Le Goater]

When skiboot initializes PSIHB, it fills the xive registers with
server=0, prio=0xff. The source (irq) value is left shifted by 29 bits
and the last two xive registers (irq 4 and 5) are set with a bogus
value :
 
	 write 0x30 val 0x000000ff00000000
	 write 0x60 val 0x000000ff20000000
	 write 0x68 val 0x000000ff40000000
	 write 0x70 val 0x000000ff60000000
	 write 0x78 val 0xffffffff80000000
	 write 0x80 val 0xffffffffa0000000

which seems to be fine for real HW but causes a lof of pain under
qemu.

Let's use an 'unsigned' type to initialize the xive registers and also
use a loop on the PSI irq numbers, like it is done in psi_cleanup_irq.

Signed-off-by: Cédric Le Goater <clg at kaod.org>
---
 hw/psi.c |   20 ++++++++------------
 1 file changed, 8 insertions(+), 12 deletions(-)

Index: skiboot.git/hw/psi.c
===================================================================
--- skiboot.git.orig/hw/psi.c
+++ skiboot.git/hw/psi.c
@@ -702,6 +702,9 @@ static void psi_init_p7_interrupt(struct
 
 static void psi_init_p8_interrupts(struct psi *psi)
 {
+	uint32_t irq;
+	uint64_t xivr_p;
+
 	/* On P8 we get a block of 8, set up the base/mask
 	 * and mask all the sources for now
 	 */
@@ -710,18 +713,11 @@ static void psi_init_p8_interrupts(struc
 		 SETFIELD(PSIHB_IRSN_MASK, 0ul, 0x7fff8ul) |
 		 PSIHB_IRSN_DOWNSTREAM_EN |
 		 PSIHB_IRSN_UPSTREAM_EN);
-	out_be64(psi->regs + PSIHB_XIVR_FSP,
-		 (0xffull << 32) | (P8_IRQ_PSI_FSP << 29));
-	out_be64(psi->regs + PSIHB_XIVR_OCC,
-		 (0xffull << 32) | (P8_IRQ_PSI_OCC << 29));
-	out_be64(psi->regs + PSIHB_XIVR_FSI,
-		 (0xffull << 32) | (P8_IRQ_PSI_FSI << 29));
-	out_be64(psi->regs + PSIHB_XIVR_LPC,
-		 (0xffull << 32) | (P8_IRQ_PSI_LPC << 29));
-	out_be64(psi->regs + PSIHB_XIVR_LOCAL_ERR,
-		 (0xffull << 32) | (P8_IRQ_PSI_LOCAL_ERR << 29));
-	out_be64(psi->regs + PSIHB_XIVR_HOST_ERR,
-		 (0xffull << 32) | (P8_IRQ_PSI_EXTERNAL << 29));
+
+	for (irq = 0; irq < P8_IRQ_PSI_IRQ_COUNT; irq++) {
+		xivr_p = psi_p8_irq_to_xivr[irq];
+		out_be64(psi->regs  + xivr_p, (0xffull << 32) | (irq << 29));
+	}
 
 	/*
 	 * Register the IRQ sources FSP, OCC, FSI, LPC