[Skiboot] [PATCH v2] pci: Avoid hot reset after post-fundamental reset

[Gavin Shan]

On Tue, Oct 11, 2016 at 04:04:07PM +1100, Russell Currey wrote:
>In the PCI post-fundamental reset code, a hot reset is performed at the
>end.  This is causing issues at boot time as a reset signal is being sent
>downstream before the links are up, which is causing issues on adapters
>behind switches.  No errors result in skiboot, but the adapters are not
>usable in Linux as a result.
>
>This patch fixes some adapters not being configurable in Linux on some
>systems.  The issue was not present in skiboot 5.2.x.
>
>Cc: stable # 5.3.x
>Signed-off-by: Russell Currey <ruscur at russell.cc>

It seems one pointed missed from last comments: firenze_pci_slot_freset()
need similar thing to skip hot reset. With this fixed:

Acked-by: Gavin Shan <gwshan at linux.vnet.ibm.com>

Thanks,
Gavin

>---
> hw/p7ioc-phb.c | 4 ++--
> hw/phb3.c      | 4 ++--
> hw/phb4.c      | 8 --------
> 3 files changed, 4 insertions(+), 12 deletions(-)
>
>diff --git a/hw/p7ioc-phb.c b/hw/p7ioc-phb.c
>index d2a18a3..1f1b362 100644
>--- a/hw/p7ioc-phb.c
>+++ b/hw/p7ioc-phb.c
>@@ -2234,8 +2234,8 @@ static int64_t p7ioc_freset(struct pci_slot *slot)
> 			return slot->ops.pfreset(slot);
> 		}
> 
>-		pci_slot_set_state(slot, P7IOC_SLOT_HRESET_START);
>-		return slot->ops.hreset(slot);
>+		pci_slot_set_state(slot, P7IOC_SLOT_LINK_START);
>+		return slot->ops.poll_link(slot);
> 	default:
> 		PHBERR(p, "FRESET: Unexpected slot state %08x\n",
> 		       slot->state);
>diff --git a/hw/phb3.c b/hw/phb3.c
>index d0b5010..817137b 100644
>--- a/hw/phb3.c
>+++ b/hw/phb3.c
>@@ -2240,8 +2240,8 @@ static int64_t phb3_pfreset(struct pci_slot *slot)
> 		/* CAPP FPGA requires 1s to flash before polling link */
> 		return pci_slot_set_sm_timeout(slot, secs_to_tb(1));
> 	case PHB3_SLOT_PFRESET_DEASSERT_DELAY:
>-		pci_slot_set_state(slot, PHB3_SLOT_HRESET_START);
>-		return slot->ops.hreset(slot);
>+		pci_slot_set_state(slot, PHB3_SLOT_LINK_START);
>+		return slot->ops.poll_link(slot);
> 	default:
> 		PHBERR(p, "Unexpected slot state %08x\n", slot->state);
> 	}
>diff --git a/hw/phb4.c b/hw/phb4.c
>index 385ce8c..efb6a5f 100644
>--- a/hw/phb4.c
>+++ b/hw/phb4.c
>@@ -1951,16 +1951,8 @@ static int64_t phb4_pfreset(struct pci_slot *slot)
> 		/* CAPP FPGA requires 1s to flash before polling link */
> 		return pci_slot_set_sm_timeout(slot, secs_to_tb(1));
> 	case PHB4_SLOT_PFRESET_DEASSERT_DELAY:
>-#if 0 	/* PHB3 does a Hreset here. It's unnecessary I think and it's
>-	 * causing problems with the simulator croc model so don't do
>-	 * it until I figure out Gavin's reasons
>-	 */
>-		pci_slot_set_state(slot, PHB4_SLOT_HRESET_START);
>-		return slot->ops.hreset(slot);
>-#else
> 		pci_slot_set_state(slot, PHB4_SLOT_LINK_START);
> 		return slot->ops.poll_link(slot);
>-#endif
> 	default:
> 		PHBERR(p, "Unexpected slot state %08x\n", slot->state);
> 	}
>-- 
>2.10.0
>
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