[Skiboot] [PATCH v2 1/7] skiboot: Nest IMA macro definitions
Oliver O'Halloran
oohall at gmail.com
Tue Nov 22 12:02:44 AEDT 2016
On Fri, Nov 18, 2016 at 1:10 PM, Hemant Kumar <hemant at linux.vnet.ibm.com> wrote:
> Add the macros needed for Nest IMA (In Memory Accumulation)
> instrumentation support by creating a new file in include/ called
> "ima.h". Also, add a header "nest_ima.h" containing an array of
> possible list of nest PMUs. These macros are needed to discover the
> catalog subpartition, enable and disable the nest IMA instrumentation.
>
> Signed-off-by: Hemant Kumar <hemant at linux.vnet.ibm.com>
> ---
> Changelog :
> v1 -> v2:
> - Changed macro names SLW_IMA_* to NEST_IMA_*.
> - Also, added a couple of new members to the IMA control block struct.
> One for run_mode and another for nest IMA PMU availability.
> - Added a new file which contains the nest IMA PMUs names and their
> definitions (will be used to check the availability).
>
> include/ima.h | 112 +++++++++++++++++++++++++++++++++++++++++++++
> include/nest_ima.h | 130 +++++++++++++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 242 insertions(+)
> create mode 100644 include/ima.h
> create mode 100644 include/nest_ima.h
>
> diff --git a/include/ima.h b/include/ima.h
> new file mode 100644
> index 0000000..f628ee0
> --- /dev/null
> +++ b/include/ima.h
> @@ -0,0 +1,112 @@
> +/* Copyright 2016 IBM Corp.
> + *
> + * Licensed under the Apache License, Version 2.0 (the "License");
> + * you may not use this file except in compliance with the License.
> + * You may obtain a copy of the License at
> + *
> + * http://www.apache.org/licenses/LICENSE-2.0
> + *
> + * Unless required by applicable law or agreed to in writing, software
> + * distributed under the License is distributed on an "AS IS" BASIS,
> + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
> + * implied.
> + * See the License for the specific language governing permissions and
> + * limitations under the License.
> + */
> +
> +/*
> + * IMA (In Memory Accumulation) Instrumentation :
> + * Power9 has IMA instrumentation support with which several metrics of
> + * the platform can be monitored. These metrics are backed by the IMA
> + * Performance Monitoring Units and their counters. They are named as IMA
> + * counters, as the counter data from these counters are fed directly
> + * into a pre-defined memory location.
> + *
> + * Depending on their location and monitoring engines, they are classified
> + * into three domains :
> + * Nest IMA, core IMA and thread IMA.
> + *
> + * Nest counters are per-chip counters and can help in providing utilisation
> + * metrics like memory bandwidth, Xlink/Alink bandwidth etc.
> + *
> + * A microcode in OCC programs the nest counters and moves counter values to
> + * per chip HOMER region in a fixed offset for each unit. Engine has a
> + * control block structure for communication with Hyperviosr(Host OS).
Spelling
> + */
> +
> +#ifndef __IMA_H
> +#define __IMA_H
> +
> +/*
> + * Control Block structure offset in HOMER IMA Region
> + */
> +#define CB_STRUCT_OFFSET 0x39FC00
> +#define CB_STRUCT_CMD 0x39FC08
> +#define CB_STRUCT_SPEED 0x39FC10
> +#define NEST_IMA_PAUSE 0x2
> +#define NEST_IMA_RESUME 0x1
> +#define NEST_IMA_NOP 0
> +
> +/*
> + * Control Block Structure:
> + *
> + * Name Producer Consumer Values Desc
> + * IMARunStatus IMA Code Hypervisor 0 Initializing
> + * (Host OS) 1 Running
> + * 2 Paused
> + *
> + * IMACommand Hypervisor IMA Code 0 NOP
> + * 1 Resume
> + * 2 Pause
> + * 3 Clear and Restart
> + *
> + * IMACollection Hypervisor IMA Code 0 128us
> + * Speed 1 256us
> + * 2 1ms
> + * 3 4ms
> + * 4 16ms
> + * 5 64ms
> + * 6 256ms
> + * 7 1000ms
> + *
> + * IMAAvailability IMA Code Hypervisor - 64-bit value describes
> + * the Vector Nest PMU
> + * availability.
> + * Bits 0-37 denote the
> + * availability of 38 different
> + * nest units.
> + * Rest are reserved. Details
> + * regarding which bit belongs
> + * to which unit, see
> + * the definitions of all
> + * the possible nest IMA
> + * PMUs.
> + *
> + * IMARun Mode Hypervisor IMA Code 0 Normal Mode (Monitor Mode)
> + * 1 Debug Mode 1 (PB)
> + * 2 Debug Mode 2 (MEM)
> + * 3 Debug Mode 3 (PCIE)
> + * 4 Debug Mode 4 (CAPP)
> + * 5 Debug Mode 5 (NPU 1)
> + * 6 Debug Mode 6 (NPU 2)
> + */
> +struct ima_chip_cb
> +{
> + u64 ima_chip_run_status;
> + u64 ima_chip_command;
> + u64 ima_chip_collection_speed;
> + u64 ima_chip_avl_vector;
> + u64 ima_chip_run_mode;
> +};
> +
> +/* Size of IMA dtb LID (256KBytes) */
> +#define IMA_DTB_SIZE 0x40000
> +
> +/*
> + * Nest IMA operations
> + */
> +#define NEST_IMA_PRODUCTION_MODE 0x1
> +#define NEST_IMA_ENABLE 0x1
> +#define NEST_IMA_DISABLE 0x2
> +
> +#endif /* __IMA_H */
> diff --git a/include/nest_ima.h b/include/nest_ima.h
> new file mode 100644
> index 0000000..d91c889
> --- /dev/null
> +++ b/include/nest_ima.h
> @@ -0,0 +1,130 @@
> +/* Copyright 2016 IBM Corp.
> + *
> + * Licensed under the Apache License, Version 2.0 (the "License");
> + * you may not use this file except in compliance with the License.
> + * You may obtain a copy of the License at
> + *
> + * http://www.apache.org/licenses/LICENSE-2.0
> + *
> + * Unless required by applicable law or agreed to in writing, software
> + * distributed under the License is distributed on an "AS IS" BASIS,
> + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
> + * implied.
> + * See the License for the specific language governing permissions and
> + * limitations under the License.
> + */
> +
> +#ifndef __NEST_IMA_H
> +#define __NEST_IMA_H
> +
> +/*
> + * Nest IMA PMU names along with their bit values as represented in the
> + * ima_chip_avl_vector(in struct ima_chip_cb, look at include/ima.h).
What does the contents of ima_chip_avl_vector actually mean? Is it a
bit field that indicates what
> + */
> +#define PB "pb" /* 0 */
> +#define MCS0 "mcs0" /* 1 */
> +#define MCS1 "mcs1" /* 2 */
> +#define MCS2 "mcs2" /* 3 */
> +#define MCS3 "mcs3" /* 4 */
> +#define MCS4 "mcs4" /* 5 */
> +#define MCS5 "mcs5" /* 6 */
> +#define MCS6 "mcs6" /* 7 */
> +#define MCS7 "mcs7" /* 8 */
> +#define MBA0 "mba0" /* 9 */
> +#define MBA1 "mba1" /* 10 */
> +#define MBA2 "mba2" /* 11 */
> +#define MBA3 "mba3" /* 12 */
> +#define MBA4 "mba4" /* 13 */
> +#define MBA5 "mba5" /* 14 */
> +#define MBA6 "mba6" /* 15 */
> +#define MBA7 "mba7" /* 16 */
> +#define CEN0 "cen0" /* 17 */
> +#define CEN1 "cen1" /* 18 */
> +#define CEN2 "cen2" /* 19 */
> +#define CEN3 "cen3" /* 20 */
> +#define CEN4 "cen4" /* 21 */
> +#define CEN5 "cen5" /* 22 */
> +#define CEN6 "cen6" /* 23 */
> +#define CEN7 "cen7" /* 24 */
> +#define XLINKS0 "xlinks0" /* 25 */
> +#define XLINKS1 "xlinks1" /* 26 */
> +#define XLINKS2 "xlinks2" /* 27 */
> +#define MCD0 "mcd0" /* 28 */
> +#define MCD1 "mcd1" /* 29 */
> +#define PHB0 "phb0" /* 30 */
> +#define PHB1 "phb1" /* 31 */
> +#define PHB2 "phb2" /* 32 */
> +#define RESVD "resvd" /* 33 */
> +#define NX "nx" /* 34 */
> +#define CAPP0 "capp0" /* 35 */
> +#define CAPP1 "capp1" /* 36 */
> +#define VAS "vas" /* 37 */
> +#define INT "int" /* 38 */
> +#define ALINKS0 "alinks0" /* 39 */
> +#define ALINKS1 "alinks1" /* 40 */
> +#define ALINKS2 "alinks2" /* 41 */
> +#define NVLINKS0 "nvlinks0" /* 42 */
> +#define NVLINKS1 "nvlinks1" /* 43 */
> +#define NVLINKS2 "nvlinks2" /* 44 */
> +#define NVLINKS3 "nvlinks3" /* 45 */
> +#define NVLINKS4 "nvlinks4" /* 46 */
> +#define NVLINKS5 "nvlinks5" /* 47 */
Why do we need any of these #defines? It looks like they could all be
folded into the array definition below.
> +/* Reserved bits : 48-64 */
> +
> +#define MAX_AVL 48
> +
> +/*
> + * An array containing all the possible nest IMA PMU nodes.
> + */
> +char const *nest_pmus[] = {
> + PB,
> + MCS0,
> + MCS1,
> + MCS2,
> + MCS3,
> + MCS4,
> + MCS5,
> + MCS6,
> + MCS7,
> + MBA0,
> + MBA1,
> + MBA2,
> + MBA3,
> + MBA4,
> + MBA5,
> + MBA6,
> + MBA7,
> + CEN0,
> + CEN1,
> + CEN2,
> + CEN3,
> + CEN4,
> + CEN5,
> + CEN6,
> + CEN7,
> + XLINKS0,
> + XLINKS1,
> + XLINKS2,
> + MCD0,
> + MCD1,
> + PHB0,
> + PHB1,
> + PHB2,
> + RESVD,
> + NX,
> + CAPP0,
> + CAPP1,
> + VAS,
> + INT,
> + ALINKS0,
> + ALINKS1,
> + ALINKS2,
> + NVLINKS0,
> + NVLINKS1,
> + NVLINKS2,
> + NVLINKS3,
> + NVLINKS4,
> + NVLINKS5,
> +};
> +
> +#endif /* __NEST_IMA_H */
> --
> 2.7.4
>
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