[Skiboot] [PATCH 1/2] core/pci: Don't check device and its PCIe cap in pcie_slot_create()

[Gavin Shan]

The PCI device and its PCIe capability position are all valid when
PCICAP_EXP_SOLTCAP_PWCTRL is set in the cached PCI slot capability.
So it's unnecessary to validate device and its PCIe capability
before updating the cached PCI slot's power state.

This removes the unnecessary check. The PCIe capability position
is fetched again to avoid building waring. The output I expect
from the code change is to make the code shorter horizontally.
So no functional changes introduced by this.

Signed-off-by: Gavin Shan <gwshan at linux.vnet.ibm.com>
---
 core/pcie-slot.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/core/pcie-slot.c b/core/pcie-slot.c
index f9bef64..109d2cb 100644
--- a/core/pcie-slot.c
+++ b/core/pcie-slot.c
@@ -450,12 +450,12 @@ struct pci_slot *pcie_slot_create(struct phb *phb, struct pci_device *pd)
 
 		/* The power is on by default */
 		slot->power_state = PCI_SLOT_POWER_ON;
-		if (pd && ecap) {
-			pci_cfg_read16(phb, pd->bdfn,
-				       ecap + PCICAP_EXP_SLOTCTL, &slot_ctl);
-			if (slot_ctl & PCICAP_EXP_SLOTCTL_PWRCTLR)
-				slot->power_state = PCI_SLOT_POWER_OFF;
-		}
+
+		ecap = pci_cap(pd, PCI_CFG_CAP_ID_EXP, false);
+		pci_cfg_read16(phb, pd->bdfn,
+			       ecap + PCICAP_EXP_SLOTCTL, &slot_ctl);
+		if (slot_ctl & PCICAP_EXP_SLOTCTL_PWRCTLR)
+			slot->power_state = PCI_SLOT_POWER_OFF;
 	}
 
 	if (slot->slot_cap & PCICAP_EXP_SLOTCAP_PWRI)
-- 
2.1.0