[Skiboot] [PATCH 1/3] phb4: Fix location of EEH enable bits

[Michael Neuling]

Fix some of the bit definitions.

Signed-off-by: Michael Neuling <mikey at neuling.org>
---
 hw/phb4.c           | 2 +-
 include/phb4-regs.h | 3 ++-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/hw/phb4.c b/hw/phb4.c
index faeefbbbae..3ebd303985 100644
--- a/hw/phb4.c
+++ b/hw/phb4.c
@@ -2712,7 +2712,7 @@ static void phb4_init_hw(struct phb4 *p, bool first_init)
 	/* Init_16 - PHB Control */
 	out_be64(p->regs + PHB_CTRLR,
 		 PHB_CTRLR_IRQ_PGSZ_64K |
-		 PHB_CTRLR_CFG_EEH_DISABLE | /* EEH disable for now ! */
+		 PHB_CTRLR_MMIO_EEH_DISABLE | /* EEH disable for now ! */
 		 SETFIELD(PHB_CTRLR_TVT_ADDR_SEL, 0ull, TVT_2_PER_PE));
 
 	/* Init_17..40 - Architected IODA3 inits */
diff --git a/include/phb4-regs.h b/include/phb4-regs.h
index 16f30f652d..48953e4040 100644
--- a/include/phb4-regs.h
+++ b/include/phb4-regs.h
@@ -125,7 +125,8 @@
 #define PHB_CTRLR			0x810
 #define   PHB_CTRLR_IRQ_PGSZ_64K	PPC_BIT(11)
 #define   PHB_CTRLR_MMIO_RD_STRICT	PPC_BIT(13)
-#define   PHB_CTRLR_CFG_EEH_DISABLE	PPC_BIT(15)
+#define   PHB_CTRLR_MMIO_EEH_DISABLE	PPC_BIT(14)
+#define   PHB_CTRLR_CFG_EEH_BLOCK	PPC_BIT(15)
 #define   PHB_CTRLR_FENCE_LNKILL_DIS	PPC_BIT(16)
 #define   PHB_CTRLR_TVT_ADDR_SEL	PPC_BITMASK(17,19)
 #define     TVT_1_PER_PE		0
-- 
2.9.3