[Skiboot] [PATCH] pci: Always print PHB and PE numbers as hexadecimal
Russell Currey
ruscur at russell.cc
Wed Nov 16 15:04:23 AEDT 2016
PHB and PE numbers are sometimes printed as decimal and sometimes as
hexadecimal, which is confusing. Standardise on hexadecimal.
This is especially useful now that PHB numbers in Linux always match
their OPAL ID.
Signed-off-by: Russell Currey <ruscur at russell.cc>
---
I have a similar patch for the kernel here:
https://patchwork.ozlabs.org/patch/695410/
---
core/pci.c | 4 ++--
hw/p7ioc-phb.c | 6 +++---
hw/phb3.c | 34 +++++++++++++++++-----------------
hw/phb4.c | 26 +++++++++++++-------------
4 files changed, 35 insertions(+), 35 deletions(-)
diff --git a/core/pci.c b/core/pci.c
index 4160299..0a9f8cd 100644
--- a/core/pci.c
+++ b/core/pci.c
@@ -880,12 +880,12 @@ int64_t pci_register_phb(struct phb *phb, int opal_id)
}
} else {
if (opal_id >= ARRAY_SIZE(phbs)) {
- prerror("PHB: ID %d out of range !\n", opal_id);
+ prerror("PHB: ID %x out of range !\n", opal_id);
return OPAL_PARAMETER;
}
/* The user did specify an opal_id, check it's free */
if (phbs[opal_id]) {
- prerror("PHB: Duplicate registration of ID %d\n", opal_id);
+ prerror("PHB: Duplicate registration of ID %x\n", opal_id);
return OPAL_PARAMETER;
}
}
diff --git a/hw/p7ioc-phb.c b/hw/p7ioc-phb.c
index 50608e2..be0225b 100644
--- a/hw/p7ioc-phb.c
+++ b/hw/p7ioc-phb.c
@@ -1857,7 +1857,7 @@ static int64_t p7ioc_ioda_reset(struct phb *phb, bool purge)
if ((pesta & IODA_PESTA_MMIO_FROZEN) ||
(pestb & IODA_PESTB_DMA_STOPPED))
- PHBDBG(p, "Frozen PE#%d (%s - %s)\n",
+ PHBDBG(p, "Frozen PE#%x (%s - %s)\n",
i, (pestb & IODA_PESTB_DMA_STOPPED) ? "DMA" : "",
(pesta & IODA_PESTA_MMIO_FROZEN) ? "MMIO" : "");
}
@@ -2682,7 +2682,7 @@ void p7ioc_phb_setup(struct p7ioc *ioc, uint8_t index)
pci_register_phb(&p->phb, OPAL_DYNAMIC_PHB_ID);
slot = p7ioc_phb_slot_create(&p->phb);
if (!slot)
- prlog(PR_NOTICE, "P7IOC: Cannot create PHB#%d slot\n",
+ prlog(PR_NOTICE, "P7IOC: Cannot create PHB#%x slot\n",
p->phb.opal_id);
/* Platform additional setup */
@@ -2957,7 +2957,7 @@ int64_t p7ioc_phb_init(struct p7ioc_phb *p)
{
uint64_t val;
- PHBDBG(p, "Initializing PHB %d...\n", p->index);
+ PHBDBG(p, "Initializing PHB %x...\n", p->index);
p->state = P7IOC_PHB_STATE_INITIALIZING;
diff --git a/hw/phb3.c b/hw/phb3.c
index 52b30c2..bd865cb 100644
--- a/hw/phb3.c
+++ b/hw/phb3.c
@@ -683,7 +683,7 @@ static int64_t phb3_ioda_reset(struct phb *phb, bool purge)
uint32_t i;
if (purge) {
- prlog(PR_DEBUG, "PHB%d: Purging all IODA tables...\n",
+ prlog(PR_DEBUG, "PHB%x: Purging all IODA tables...\n",
p->phb.opal_id);
phb3_init_ioda_cache(p);
}
@@ -757,7 +757,7 @@ static int64_t phb3_ioda_reset(struct phb *phb, bool purge)
if ((pesta & IODA2_PESTA_MMIO_FROZEN) ||
(pestb & IODA2_PESTB_DMA_STOPPED))
- PHBDBG(p, "Frozen PE#%d (%s - %s)\n",
+ PHBDBG(p, "Frozen PE#%x (%s - %s)\n",
i, (pesta & IODA2_PESTA_MMIO_FROZEN) ? "DMA" : "",
(pestb & IODA2_PESTB_DMA_STOPPED) ? "MMIO" : "");
}
@@ -4563,18 +4563,18 @@ static void phb3_probe_pbcq(struct dt_node *pbcq)
pe_xscom = dt_get_address(pbcq, 0, NULL);
pci_xscom = dt_get_address(pbcq, 1, NULL);
spci_xscom = dt_get_address(pbcq, 2, NULL);
- prlog(PR_DEBUG, "PHB3[%d:%d]: X[PE]=0x%08x X[PCI]=0x%08x"
+ prlog(PR_DEBUG, "PHB3[%x:%x]: X[PE]=0x%08x X[PCI]=0x%08x"
" X[SPCI]=0x%08x\n",
gcid, pno, pe_xscom, pci_xscom, spci_xscom);
/* Check if CAPP mode */
if (xscom_read(gcid, spci_xscom + 0x03, &val)) {
- prerror("PHB3[%d:%d]: Cannot read AIB CAPP ENABLE\n",
+ prerror("PHB3[%x:%x]: Cannot read AIB CAPP ENABLE\n",
gcid, pno);
return;
}
if (val >> 63) {
- prerror("PHB3[%d:%d]: Ignoring bridge in CAPP mode\n",
+ prerror("PHB3[%x:%x]: Ignoring bridge in CAPP mode\n",
gcid, pno);
return;
}
@@ -4582,10 +4582,10 @@ static void phb3_probe_pbcq(struct dt_node *pbcq)
/* Get PE BARs, assume only 0 and 2 are used for now */
xscom_read(gcid, pe_xscom + 0x42, &phb_bar);
phb_bar >>= 14;
- prlog(PR_DEBUG, "PHB3[%d:%d] REGS = 0x%016llx [4k]\n",
+ prlog(PR_DEBUG, "PHB3[%x:%x] REGS = 0x%016llx [4k]\n",
gcid, pno, phb_bar);
if (phb_bar == 0) {
- prerror("PHB3[%d:%d]: No PHB BAR set !\n", gcid, pno);
+ prerror("PHB3[%x:%x]: No PHB BAR set !\n", gcid, pno);
return;
}
@@ -4593,9 +4593,9 @@ static void phb3_probe_pbcq(struct dt_node *pbcq)
xscom_read(gcid, spci_xscom + 1, &val);/* HW275117 */
xscom_read(gcid, pci_xscom + 0x0b, &val);
val >>= 14;
- prlog(PR_DEBUG, "PHB3[%d:%d] PCIBAR = 0x%016llx\n", gcid, pno, val);
+ prlog(PR_DEBUG, "PHB3[%x:%x] PCIBAR = 0x%016llx\n", gcid, pno, val);
if (phb_bar != val) {
- prerror("PHB3[%d:%d] PCIBAR invalid, fixing up...\n",
+ prerror("PHB3[%x:%x] PCIBAR invalid, fixing up...\n",
gcid, pno);
xscom_read(gcid, spci_xscom + 1, &val);/* HW275117 */
xscom_write(gcid, pci_xscom + 0x0b, phb_bar << 14);
@@ -4607,14 +4607,14 @@ static void phb3_probe_pbcq(struct dt_node *pbcq)
mmio0_bmask &= 0xffffffffc0000000ull;
mmio0_sz = ((~mmio0_bmask) >> 14) + 1;
mmio0_bar >>= 14;
- prlog(PR_DEBUG, "PHB3[%d:%d] MMIO0 = 0x%016llx [0x%016llx]\n",
+ prlog(PR_DEBUG, "PHB3[%x:%x] MMIO0 = 0x%016llx [0x%016llx]\n",
gcid, pno, mmio0_bar, mmio0_sz);
xscom_read(gcid, pe_xscom + 0x41, &mmio1_bar);
xscom_read(gcid, pe_xscom + 0x44, &mmio1_bmask);
mmio1_bmask &= 0xffffffffc0000000ull;
mmio1_sz = ((~mmio1_bmask) >> 14) + 1;
mmio1_bar >>= 14;
- prlog(PR_DEBUG, "PHB3[%d:%d] MMIO1 = 0x%016llx [0x%016llx]\n",
+ prlog(PR_DEBUG, "PHB3[%x:%x] MMIO1 = 0x%016llx [0x%016llx]\n",
gcid, pno, mmio1_bar, mmio1_sz);
/* Check BAR enable
@@ -4623,7 +4623,7 @@ static void phb3_probe_pbcq(struct dt_node *pbcq)
* that BARs are valid if they value is non-0
*/
xscom_read(gcid, pe_xscom + 0x45, &bar_en);
- prlog(PR_DEBUG, "PHB3[%d:%d] BAREN = 0x%016llx\n",
+ prlog(PR_DEBUG, "PHB3[%x:%x] BAREN = 0x%016llx\n",
gcid, pno, bar_en);
/* Always enable PHB BAR */
@@ -4644,7 +4644,7 @@ static void phb3_probe_pbcq(struct dt_node *pbcq)
/* No MMIO windows ? Barf ! */
if (mmio_win_sz == 0) {
- prerror("PHB3[%d:%d]: No MMIO windows enabled !\n",
+ prerror("PHB3[%x:%x]: No MMIO windows enabled !\n",
gcid, pno);
return;
}
@@ -4664,16 +4664,16 @@ static void phb3_probe_pbcq(struct dt_node *pbcq)
bar_en |= 0x1800000000000000ul;
xscom_write(gcid, pe_xscom + 0x45, bar_en);
- prlog(PR_DEBUG, "PHB3[%d:%d] NEWBAREN = 0x%016llx\n",
+ prlog(PR_DEBUG, "PHB3[%x:%x] NEWBAREN = 0x%016llx\n",
gcid, pno, bar_en);
xscom_read(gcid, pe_xscom + 0x1a, &val);
- prlog(PR_DEBUG, "PHB3[%d:%d] IRSNC = 0x%016llx\n",
+ prlog(PR_DEBUG, "PHB3[%x:%x] IRSNC = 0x%016llx\n",
gcid, pno, val);
xscom_read(gcid, pe_xscom + 0x1b, &val);
- prlog(PR_DEBUG, "PHB3[%d:%d] IRSNM = 0x%016llx\n",
+ prlog(PR_DEBUG, "PHB3[%x:%x] IRSNM = 0x%016llx\n",
gcid, pno, val);
- prlog(PR_DEBUG, "PHB3[%d:%d] LSI = 0x%016llx\n",
+ prlog(PR_DEBUG, "PHB3[%x:%x] LSI = 0x%016llx\n",
gcid, pno, val);
/* Create PHB node */
diff --git a/hw/phb4.c b/hw/phb4.c
index 0ba6392..02ef33d 100644
--- a/hw/phb4.c
+++ b/hw/phb4.c
@@ -59,11 +59,11 @@
static void phb4_init_hw(struct phb4 *p, bool first_init);
-#define PHBDBG(p, fmt, a...) prlog(PR_DEBUG, "PHB%d: " fmt, \
+#define PHBDBG(p, fmt, a...) prlog(PR_DEBUG, "PHB#%04x: " fmt, \
(p)->phb.opal_id, ## a)
-#define PHBINF(p, fmt, a...) prlog(PR_INFO, "PHB%d: " fmt, \
+#define PHBINF(p, fmt, a...) prlog(PR_INFO, "PHB#%04x: " fmt, \
(p)->phb.opal_id, ## a)
-#define PHBERR(p, fmt, a...) prlog(PR_ERR, "PHB%d: " fmt, \
+#define PHBERR(p, fmt, a...) prlog(PR_ERR, "PHB#%04x: " fmt, \
(p)->phb.opal_id, ## a)
/* Note: The "ASB" name is historical, practically this means access via
@@ -898,7 +898,7 @@ static int64_t phb4_ioda_reset(struct phb *phb, bool purge)
uint64_t val;
if (purge) {
- prlog(PR_DEBUG, "PHB%d: Purging all IODA tables...\n",
+ prlog(PR_DEBUG, "PHB%x: Purging all IODA tables...\n",
p->phb.opal_id);
phb4_init_ioda_cache(p);
}
@@ -3260,7 +3260,7 @@ static void phb4_probe_stack(struct dt_node *stk_node, uint32_t pec_index,
nest_stack = nest_base + 0x40 * (stk_index + 1);
etu_base = pci_base + 0x100 + 0x40 * stk_index;
- prlog(PR_DEBUG, "PHB4[%d:%d] X[PE]=0x%08x/0x%08x X[PCI]=0x%08x/0x%08x X[ETU]=0x%08x\n",
+ prlog(PR_DEBUG, "PHB4[%x:%x] X[PE]=0x%08x/0x%08x X[PCI]=0x%08x/0x%08x X[ETU]=0x%08x\n",
gcid, phb_num, nest_base, nest_stack, pci_base, pci_stack, etu_base);
/* Default BAR enables */
@@ -3269,7 +3269,7 @@ static void phb4_probe_stack(struct dt_node *stk_node, uint32_t pec_index,
/* Get and/or initialize PHB register BAR */
xscom_read(gcid, nest_stack + XPEC_NEST_STK_PHB_REG_BAR, &phb_bar);
if (phb_bar == 0 || force_assign) {
- prerror("PHB4[%d:%d] No PHB BAR set ! Overriding\n", gcid, phb_num);
+ prerror("PHB4[%x:%x] No PHB BAR set ! Overriding\n", gcid, phb_num);
phb_bar = MMIO_CALC(gcid, phb_num, PHB_BAR);
xscom_write(gcid, nest_stack + XPEC_NEST_STK_PHB_REG_BAR, phb_bar << 8);
}
@@ -3277,12 +3277,12 @@ static void phb4_probe_stack(struct dt_node *stk_node, uint32_t pec_index,
xscom_read(gcid, nest_stack + XPEC_NEST_STK_PHB_REG_BAR, &phb_bar);
phb_bar >>= 8;
- prlog(PR_ERR, "PHB4[%d:%d] REGS = 0x%016llx [4k]\n", gcid, phb_num, phb_bar);
+ prlog(PR_ERR, "PHB4[%x:%x] REGS = 0x%016llx [4k]\n", gcid, phb_num, phb_bar);
/* Same with INT BAR (ESB) */
xscom_read(gcid, nest_stack + XPEC_NEST_STK_IRQ_BAR, &irq_bar);
if (irq_bar == 0 || force_assign) {
- prerror("PHB4[%d:%d] No IRQ BAR set ! Overriding\n", gcid, phb_num);
+ prerror("PHB4[%x:%x] No IRQ BAR set ! Overriding\n", gcid, phb_num);
irq_bar = MMIO_CALC(gcid, phb_num, ESB_BAR);
xscom_write(gcid, nest_stack + XPEC_NEST_STK_IRQ_BAR, irq_bar << 8);
}
@@ -3290,12 +3290,12 @@ static void phb4_probe_stack(struct dt_node *stk_node, uint32_t pec_index,
xscom_read(gcid, nest_stack + XPEC_NEST_STK_IRQ_BAR, &irq_bar);
irq_bar >>= 8;
- prlog(PR_ERR, "PHB4[%d:%d] ESB = 0x%016llx [...]\n", gcid, phb_num, irq_bar);
+ prlog(PR_ERR, "PHB4[%x:%x] ESB = 0x%016llx [...]\n", gcid, phb_num, irq_bar);
/* Same with MMIO windows */
xscom_read(gcid, nest_stack + XPEC_NEST_STK_MMIO_BAR0, &mmio0_bar);
if (mmio0_bar == 0 || force_assign) {
- prerror("PHB4[%d:%d] No MMIO BAR set ! Overriding\n", gcid, phb_num);
+ prerror("PHB4[%x:%x] No MMIO BAR set ! Overriding\n", gcid, phb_num);
mmio0_bar = MMIO_CALC(gcid, phb_num, MMIO0_BAR);
mmio0_bmask = (~(MMIO0_BAR_SIZE - 1)) & 0x00FFFFFFFFFFFFFFULL;
xscom_write(gcid, nest_stack + XPEC_NEST_STK_MMIO_BAR0, mmio0_bar << 8);
@@ -3313,7 +3313,7 @@ static void phb4_probe_stack(struct dt_node *stk_node, uint32_t pec_index,
mmio0_bmask &= 0xffffffffff000000ull;
mmio0_sz = ((~mmio0_bmask) >> 8) + 1;
mmio0_bar >>= 8;
- prlog(PR_DEBUG, "PHB4[%d:%d] MMIO0 = 0x%016llx [0x%016llx]\n",
+ prlog(PR_DEBUG, "PHB4[%x:%x] MMIO0 = 0x%016llx [0x%016llx]\n",
gcid, phb_num, mmio0_bar, mmio0_sz);
xscom_read(gcid, nest_stack + XPEC_NEST_STK_MMIO_BAR1, &mmio1_bar);
@@ -3321,7 +3321,7 @@ static void phb4_probe_stack(struct dt_node *stk_node, uint32_t pec_index,
mmio1_bmask &= 0xffffffffff000000ull;
mmio1_sz = ((~mmio1_bmask) >> 8) + 1;
mmio1_bar >>= 8;
- prlog(PR_DEBUG, "PHB4[%d:%d] MMIO1 = 0x%016llx [0x%016llx]\n",
+ prlog(PR_DEBUG, "PHB4[%x:%x] MMIO1 = 0x%016llx [0x%016llx]\n",
gcid, phb_num, mmio1_bar, mmio1_sz);
/* Build MMIO windows list */
@@ -3344,7 +3344,7 @@ static void phb4_probe_stack(struct dt_node *stk_node, uint32_t pec_index,
/* No MMIO windows ? Barf ! */
if (mmio_win_sz == 0) {
- prerror("PHB4[%d:%d] No MMIO windows enabled !\n", gcid, phb_num);
+ prerror("PHB4[%x:%x] No MMIO windows enabled !\n", gcid, phb_num);
return;
}
--
2.10.2
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