[Skiboot] [PATCH] Added a 5ms wait after a msi-irq is masked

[Michael Neuling]

On Tue, 2016-03-22 at 11:46 +0100, Philippe Bergheaud wrote:
> From: Vaibhav Jain <vaibhav at linux.vnet.ibm.com>
> 
> Adds a 5ms wait to phb3_msi_set_xive after the interrupt is masked so
> that the kernel delays cleanup until an irq if its in-flight is
> handled. The value 5ms is the worst case time needed by an irq to be
> presented to the host after its generated.

I don't think we can do this here.  We can't have firmware
take a CPU for 5ms.

I think we need to do this workaround in Linux.

Mikey

> 
> Signed-off-by: Vaibhav Jain <vaibhav at linux.vnet.ibm.com>
> ---
> This patch requires the following patches:
> https://patchwork.ozlabs.org/patch/581764/
> https://patchwork.ozlabs.org/patch/581765/

> 
>  hw/phb3.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/hw/phb3.c b/hw/phb3.c
> index fbdcb9e..e5d49b2 100644
> --- a/hw/phb3.c
> +++ b/hw/phb3.c
> @@ -1751,6 +1751,8 @@ static int64_t phb3_msi_set_xive(void *data,
>  			PHB_IVC_UPDATE_ENABLE_Q |
>  			PHB_IVC_UPDATE_ENABLE_GEN;
>  		out_be64(p->regs + PHB_IVC_UPDATE, ivc);
> +		/* wait for 5ms before signalling the interrupt is masked */

This would need a longer explanation as to why.

> +		time_wait_ms(5);
>  	}
>  
>  	return OPAL_SUCCESS;