[Skiboot] [PATCH] hw/lpc: LPC driver code improvements
Vipin K Parashar
vipin at linux.vnet.ibm.com
Mon Jun 20 21:40:29 AEST 2016
Use pr_fmt macro for LPC driver log messages. Also corrected
indentation at few places and changed printfs to use prlog.
Signed-off-by: Vipin K Parashar <vipin at linux.vnet.ibm.com>
---
hw/lpc.c | 133 ++++++++++++++++++++++++++++++++-------------------------------
1 file changed, 68 insertions(+), 65 deletions(-)
diff --git a/hw/lpc.c b/hw/lpc.c
index d2a72f1..0b80a95 100644
--- a/hw/lpc.c
+++ b/hw/lpc.c
@@ -14,6 +14,8 @@
* limitations under the License.
*/
+#define pr_fmt(fmt) "LPC: " fmt
+
#include <skiboot.h>
#include <xscom.h>
#include <io.h>
@@ -47,7 +49,7 @@ DEFINE_LOG_ENTRY(OPAL_RC_LPC_SYNC, OPAL_PLATFORM_ERR_EVT, OPAL_LPC,
#define ECCB_CTL_DATASZ PPC_BITMASK(4,7)
#define ECCB_CTL_READ PPC_BIT(15)
#define ECCB_CTL_ADDRLEN PPC_BITMASK(23,25)
-#define ECCB_ADDRLEN_4B 0x4
+#define ECCB_ADDRLEN_4B 0x4
#define ECCB_CTL_ADDR PPC_BITMASK(32,63)
#define ECCB_STAT_PIB_ERR PPC_BITMASK(0,5)
@@ -61,52 +63,52 @@ DEFINE_LOG_ENTRY(OPAL_RC_LPC_SYNC, OPAL_PLATFORM_ERR_EVT, OPAL_LPC,
ECCB_STAT_ERRORS1 | \
ECCB_STAT_ERRORS2)
-#define ECCB_TIMEOUT 1000000
+#define ECCB_TIMEOUT 1000000
/* OPB Master LS registers */
-#define OPB_MASTER_LS_IRQ_STAT 0x50
-#define OPB_MASTER_LS_IRQ_MASK 0x54
-#define OPB_MASTER_LS_IRQ_POL 0x58
-#define OPB_MASTER_IRQ_LPC 0x00000800
+#define OPB_MASTER_LS_IRQ_STAT 0x50
+#define OPB_MASTER_LS_IRQ_MASK 0x54
+#define OPB_MASTER_LS_IRQ_POL 0x58
+#define OPB_MASTER_IRQ_LPC 0x00000800
/* LPC HC registers */
-#define LPC_HC_FW_SEG_IDSEL 0x24
-#define LPC_HC_FW_RD_ACC_SIZE 0x28
-#define LPC_HC_FW_RD_1B 0x00000000
-#define LPC_HC_FW_RD_2B 0x01000000
-#define LPC_HC_FW_RD_4B 0x02000000
-#define LPC_HC_FW_RD_16B 0x04000000
-#define LPC_HC_FW_RD_128B 0x07000000
-#define LPC_HC_IRQSER_CTRL 0x30
-#define LPC_HC_IRQSER_EN 0x80000000
-#define LPC_HC_IRQSER_QMODE 0x40000000
-#define LPC_HC_IRQSER_START_MASK 0x03000000
-#define LPC_HC_IRQSER_START_4CLK 0x00000000
-#define LPC_HC_IRQSER_START_6CLK 0x01000000
-#define LPC_HC_IRQSER_START_8CLK 0x02000000
-#define LPC_HC_IRQMASK 0x34 /* same bit defs as LPC_HC_IRQSTAT */
-#define LPC_HC_IRQSTAT 0x38
-#define LPC_HC_IRQ_SERIRQ0 0x80000000 /* all bits down to ... */
-#define LPC_HC_IRQ_SERIRQ16 0x00008000 /* IRQ16=IOCHK#, IRQ2=SMI# */
-#define LPC_HC_IRQ_SERIRQ_ALL 0xffff8000
-#define LPC_HC_IRQ_LRESET 0x00000400
-#define LPC_HC_IRQ_SYNC_ABNORM_ERR 0x00000080
-#define LPC_HC_IRQ_SYNC_NORESP_ERR 0x00000040
-#define LPC_HC_IRQ_SYNC_NORM_ERR 0x00000020
-#define LPC_HC_IRQ_SYNC_TIMEOUT_ERR 0x00000010
-#define LPC_HC_IRQ_TARG_TAR_ERR 0x00000008
-#define LPC_HC_IRQ_BM_TAR_ERR 0x00000004
-#define LPC_HC_IRQ_BM0_REQ 0x00000002
-#define LPC_HC_IRQ_BM1_REQ 0x00000001
-#define LPC_HC_IRQ_BASE_IRQS ( \
- LPC_HC_IRQ_LRESET | \
- LPC_HC_IRQ_SYNC_ABNORM_ERR | \
- LPC_HC_IRQ_SYNC_NORESP_ERR | \
- LPC_HC_IRQ_SYNC_NORM_ERR | \
- LPC_HC_IRQ_SYNC_TIMEOUT_ERR | \
- LPC_HC_IRQ_TARG_TAR_ERR | \
- LPC_HC_IRQ_BM_TAR_ERR)
-#define LPC_HC_ERROR_ADDRESS 0x40
+#define LPC_HC_FW_SEG_IDSEL 0x24
+#define LPC_HC_FW_RD_ACC_SIZE 0x28
+#define LPC_HC_FW_RD_1B 0x00000000
+#define LPC_HC_FW_RD_2B 0x01000000
+#define LPC_HC_FW_RD_4B 0x02000000
+#define LPC_HC_FW_RD_16B 0x04000000
+#define LPC_HC_FW_RD_128B 0x07000000
+#define LPC_HC_IRQSER_CTRL 0x30
+#define LPC_HC_IRQSER_EN 0x80000000
+#define LPC_HC_IRQSER_QMODE 0x40000000
+#define LPC_HC_IRQSER_START_MASK 0x03000000
+#define LPC_HC_IRQSER_START_4CLK 0x00000000
+#define LPC_HC_IRQSER_START_6CLK 0x01000000
+#define LPC_HC_IRQSER_START_8CLK 0x02000000
+#define LPC_HC_IRQMASK 0x34 /* same defs as LPC_HC_IRQSTAT */
+#define LPC_HC_IRQSTAT 0x38
+#define LPC_HC_IRQ_SERIRQ0 0x80000000 /* all bits down to ... */
+#define LPC_HC_IRQ_SERIRQ16 0x00008000 /* IRQ16=IOCHK#, IRQ2=SMI# */
+#define LPC_HC_IRQ_SERIRQ_ALL 0xffff8000
+#define LPC_HC_IRQ_LRESET 0x00000400
+#define LPC_HC_IRQ_SYNC_ABNORM_ERR 0x00000080
+#define LPC_HC_IRQ_SYNC_NORESP_ERR 0x00000040
+#define LPC_HC_IRQ_SYNC_NORM_ERR 0x00000020
+#define LPC_HC_IRQ_SYNC_TIMEOUT_ERR 0x00000010
+#define LPC_HC_IRQ_TARG_TAR_ERR 0x00000008
+#define LPC_HC_IRQ_BM_TAR_ERR 0x00000004
+#define LPC_HC_IRQ_BM0_REQ 0x00000002
+#define LPC_HC_IRQ_BM1_REQ 0x00000001
+#define LPC_HC_IRQ_BASE_IRQS ( \
+ LPC_HC_IRQ_LRESET | \
+ LPC_HC_IRQ_SYNC_ABNORM_ERR | \
+ LPC_HC_IRQ_SYNC_NORESP_ERR | \
+ LPC_HC_IRQ_SYNC_NORM_ERR | \
+ LPC_HC_IRQ_SYNC_TIMEOUT_ERR | \
+ LPC_HC_IRQ_TARG_TAR_ERR | \
+ LPC_HC_IRQ_BM_TAR_ERR)
+#define LPC_HC_ERROR_ADDRESS 0x40
struct lpc_client_entry {
struct list_node node;
@@ -145,7 +147,7 @@ static int64_t opb_write(struct proc_chip *chip, uint32_t addr, uint32_t data,
data_reg = ((uint64_t)data) << 32;
break;
default:
- prerror("LPC: Invalid data size %d\n", sz);
+ prerror("Invalid data size %d\n", sz);
return OPAL_PARAMETER;
}
@@ -195,7 +197,7 @@ static int64_t opb_read(struct proc_chip *chip, uint32_t addr, uint32_t *data,
int64_t rc, tout;
if (sz != 1 && sz != 2 && sz != 4) {
- prerror("LPC: Invalid data size %d\n", sz);
+ prerror("Invalid data size %d\n", sz);
return OPAL_PARAMETER;
}
@@ -256,14 +258,14 @@ static int64_t lpc_set_fw_idsel(struct proc_chip *chip, uint8_t idsel)
rc = opb_read(chip, lpc_reg_opb_base + LPC_HC_FW_SEG_IDSEL,
&val, 4);
if (rc) {
- prerror("LPC: Failed to read HC_FW_SEG_IDSEL register !\n");
+ prerror("Failed to read HC_FW_SEG_IDSEL register !\n");
return rc;
}
val = (val & 0xfffffff0) | idsel;
rc = opb_write(chip, lpc_reg_opb_base + LPC_HC_FW_SEG_IDSEL,
val, 4);
if (rc) {
- prerror("LPC: Failed to write HC_FW_SEG_IDSEL register !\n");
+ prerror("Failed to write HC_FW_SEG_IDSEL register !\n");
return rc;
}
chip->lpc_fw_idsel = idsel;
@@ -299,7 +301,7 @@ static int64_t lpc_set_fw_rdsz(struct proc_chip *chip, uint8_t rdsz)
rc = opb_write(chip, lpc_reg_opb_base + LPC_HC_FW_RD_ACC_SIZE,
val, 4);
if (rc) {
- prerror("LPC: Failed to write LPC_HC_FW_RD_ACC_SIZE !\n");
+ prerror("Failed to write LPC_HC_FW_RD_ACC_SIZE !\n");
return rc;
}
chip->lpc_fw_rdsz = rdsz;
@@ -508,7 +510,7 @@ static void lpc_setup_serirq(struct proc_chip *chip)
rc = opb_write(chip, lpc_reg_opb_base + LPC_HC_IRQMASK, mask, 4);
if (rc) {
- prerror("LPC: Failed to update irq mask\n");
+ prerror("Failed to update irq mask\n");
return;
}
DBG_IRQ("LPC: IRQ mask set to 0x%08x\n", mask);
@@ -518,7 +520,7 @@ static void lpc_setup_serirq(struct proc_chip *chip)
rc = opb_write(chip, opb_master_reg_base + OPB_MASTER_LS_IRQ_MASK,
OPB_MASTER_IRQ_LPC, 4);
if (rc)
- prerror("LPC: Failed to enable IRQs in OPB\n");
+ prerror("Failed to enable IRQs in OPB\n");
/* Check whether we should enable serirq */
if (mask & LPC_HC_IRQ_SERIRQ_ALL) {
@@ -531,18 +533,18 @@ static void lpc_setup_serirq(struct proc_chip *chip)
DBG_IRQ("LPC: SerIRQ disabled\n");
}
if (rc)
- prerror("LPC: Failed to configure SerIRQ\n");
+ prerror("Failed to configure SerIRQ\n");
{
u32 val;
rc = opb_read(chip, lpc_reg_opb_base + LPC_HC_IRQMASK, &val, 4);
if (rc)
- prerror("LPC: failed to readback mask");
+ prerror("Failed to readback mask");
else
DBG_IRQ("LPC: MASK READBACK=%x\n", val);
rc = opb_read(chip, lpc_reg_opb_base + LPC_HC_IRQSER_CTRL, &val, 4);
if (rc)
- prerror("LPC: failed to readback ctrl");
+ prerror("Failed to readback ctrl");
else
DBG_IRQ("LPC: CTRL READBACK=%x\n", val);
}
@@ -555,7 +557,7 @@ static void lpc_init_interrupts(struct proc_chip *chip)
/* First mask them all */
rc = opb_write(chip, lpc_reg_opb_base + LPC_HC_IRQMASK, 0, 4);
if (rc) {
- prerror("LPC: Failed to init interrutps\n");
+ prerror("Failed to init interrutps\n");
return;
}
@@ -568,7 +570,7 @@ static void lpc_init_interrupts(struct proc_chip *chip)
rc = opb_write(chip, lpc_reg_opb_base + LPC_HC_IRQMASK,
LPC_HC_IRQ_BASE_IRQS, 4);
if (rc) {
- prerror("LPC: Failed to set interrupt mask\n");
+ prerror("Failed to set interrupt mask\n");
return;
}
opb_write(chip, lpc_reg_opb_base + LPC_HC_IRQSER_CTRL, 0, 4);
@@ -599,7 +601,7 @@ static void lpc_dispatch_reset(struct proc_chip *chip)
* on/off rather than just reset
*/
- prerror("LPC: Got LPC reset !\n");
+ prerror("Got LPC reset!\n");
/* Collect serirq enable bits */
list_for_each(&chip->lpc_clients, ent, node) {
@@ -627,7 +629,7 @@ static void lpc_dispatch_err_irqs(struct proc_chip *chip, uint32_t irqs)
rc = opb_write(chip, lpc_reg_opb_base + LPC_HC_IRQSTAT,
LPC_HC_IRQ_BASE_IRQS, 4);
if (rc)
- prerror("LPC: Failed to clear IRQ error latches !\n");
+ prerror("Failed to clear IRQ error latches !\n");
if (irqs & LPC_HC_IRQ_LRESET)
lpc_dispatch_reset(chip);
@@ -648,10 +650,10 @@ static void lpc_dispatch_err_irqs(struct proc_chip *chip, uint32_t irqs)
&err_addr, 4);
if (rc)
log_simple_error(&e_info(OPAL_RC_LPC_SYNC), "%s "
- "Error reading error address register\n", sync_err);
+ "Error address: Unknown\n", sync_err);
else
log_simple_error(&e_info(OPAL_RC_LPC_SYNC), "%s "
- "Error address reg: 0x%08x\n",
+ "Error address: 0x%08x\n",
sync_err, err_addr);
}
@@ -685,7 +687,7 @@ static void lpc_dispatch_ser_irqs(struct proc_chip *chip, uint32_t irqs,
rc = opb_write(chip, lpc_reg_opb_base + LPC_HC_IRQSTAT,
irqs, 4);
if (rc)
- prerror("LPC: Failed to clear SerIRQ latches !\n");
+ prerror("Failed to clear SerIRQ latches !\n");
}
void lpc_interrupt(uint32_t chip_id)
@@ -704,7 +706,7 @@ void lpc_interrupt(uint32_t chip_id)
rc = opb_read(chip, opb_master_reg_base + OPB_MASTER_LS_IRQ_STAT,
&opb_irqs, 4);
if (rc) {
- prerror("LPC: Failed to read OPB IRQ state\n");
+ prerror("Failed to read OPB IRQ state\n");
goto bail;
}
@@ -719,7 +721,7 @@ void lpc_interrupt(uint32_t chip_id)
/* Handle the lpc interrupt source (errors etc...) */
rc = opb_read(chip, lpc_reg_opb_base + LPC_HC_IRQSTAT, &irqs, 4);
if (rc) {
- prerror("LPC: Failed to read LPC IRQ state\n");
+ prerror("Failed to read LPC IRQ state\n");
goto bail;
}
@@ -772,8 +774,8 @@ void lpc_init(void)
lpc_default_chip_id = chip->id;
}
- printf("LPC: Bus on chip %d PCB_Addr=0x%x\n",
- chip->id, chip->lpc_xbase);
+ prlog(PR_NOTICE, "Bus on chip %d PCB_Addr=0x%x\n",
+ chip->id, chip->lpc_xbase);
has_lpc = true;
lpc_init_interrupts(chip);
@@ -781,7 +783,8 @@ void lpc_init(void)
dt_add_property(xn, "interrupt-controller", NULL, 0);
}
if (lpc_default_chip_id >= 0)
- printf("LPC: Default bus on chip %d\n", lpc_default_chip_id);
+ prlog(PR_NOTICE, "Default bus on chip %d\n",
+ lpc_default_chip_id);
if (has_lpc) {
opal_register(OPAL_LPC_WRITE, opal_lpc_write, 5);
--
2.1.4
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