[Skiboot] [PATCH] phb: Work around XSL bug sending PTE updates with wrong scope

[Ian Munsie]

From: Ian Munsie <imunsie at au1.ibm.com>

The XSL incorrectly sends out PTE updates with nodal scope instead of
group scope, which causes a system checkstop. This is exacerbated by the
fact that recent Linux kernels do not set the R bit in the hashed page
tables, requiring the XSL to write them back to set that bit. Work
around this issue by forcing all commands to be unlimited scope.

This might have a slight performance impact, but it is expected to be
negligible since the XSL is only used for translations, not for block
data transfers. To avoid impacting other cards, tie it off the use of
DMA mode, as only the XSL based Mellanox CX4 card uses this mode and is
affected.

Signed-off-by: Ian Munsie <imunsie at au1.ibm.com>
---

Note that this patch depends on '[2/2] phb3: Add support for CAPP DMA mode':
http://patchwork.ozlabs.org/patch/625582/

 hw/phb3.c | 20 +++++++++++++++-----
 1 file changed, 15 insertions(+), 5 deletions(-)

diff --git a/hw/phb3.c b/hw/phb3.c
index 3bfa000..156bd9e 100644
--- a/hw/phb3.c
+++ b/hw/phb3.c
@@ -3330,15 +3330,25 @@ static void phb3_init_capp_regs(struct phb3 *p, bool dma_mode)
 	uint32_t offset;
 	uint64_t read_buffers = 0;
 
-	if (dma_mode) {
-		/* In DMA mode, the CAPP only owns some of the PHB read buffers */
-		read_buffers = 0x1;
-	}
-
 	offset = PHB3_CAPP_REG_OFFSET(p);
 	xscom_read(p->chip_id, APC_MASTER_PB_CTRL + offset, &reg);
 	reg &= ~PPC_BITMASK(10, 11);
 	reg |= PPC_BIT(3);
+	if (dma_mode) {
+		/* In DMA mode, the CAPP only owns some of the PHB read buffers */
+		read_buffers = 0x1;
+
+		/*
+		 * HW301991 - XSL sends PTE updates with nodal scope instead of
+		 * group scope. The workaround is to force all commands to
+		 * unlimited scope by setting bit 4. This may have a slight
+		 * performance impact, but it would be negligable on the XSL.
+		 * To avoid the possibility it might impact other cards, key it
+		 * off DMA mode since the XSL based Mellanox CX4 is the only
+		 * card to use this mode in P8 timeframe:
+		 */
+		reg |= PPC_BIT(4);
+	}
 	reg |= read_buffers << PPC_BITLSHIFT(11);
 	xscom_write(p->chip_id, APC_MASTER_PB_CTRL + offset, reg);
 
-- 
2.8.1