[Skiboot] [PATCH] psi: fix the xive registers initialization on P8

[Stewart Smith]

Cédric Le Goater <clg at kaod.org> writes:
> When skiboot initializes PSIHB, it fills the xive registers with
> server=0, prio=0xff. The source (irq) value is left shifted by 29 bits
> and the last two xive registers (irq 4 and 5) are set with a bogus
> value :
>
> 	 write 0x30 val 0x000000ff00000000
> 	 write 0x60 val 0x000000ff20000000
> 	 write 0x68 val 0x000000ff40000000
> 	 write 0x70 val 0x000000ff60000000
> 	 write 0x78 val 0xffffffff80000000
> 	 write 0x80 val 0xffffffffa0000000
>
> which seems to be fine for real HW but causes a lof of pain under
> qemu.
>
> Let's use an 'unsigned' type to initialize the xive registers and also
> use a loop on the PSI irq numbers, like it is done in psi_cleanup_irq.
>
> Signed-off-by: Cédric Le Goater <clg at kaod.org>

looks good, simplifies things, great!

Merged to master as of e44f3be

-- 
Stewart Smith
OPAL Architect, IBM.