[Skiboot] [PATCH v2] slw: Set PSSCR value for idle states

Stewart Smith stewart at linux.vnet.ibm.com
Wed Dec 14 17:18:15 AEDT 2016

Shilpasri G Bhat <shilpa.bhat at linux.vnet.ibm.com> writes:
> PSSCR(Processor Stop Status and Control Register) is an SPR whose
> contents control the operation of stop instruction. Currently in DT,
> the value of PSSCR only included RL(Requested Level) for each idle
> state. This patch adds MTL(Maximum Transistion Level), TR(Transistion
> Rate), ESL(Enable State Loss) and EC(Exit Criterion) bits for idle
> state in the PSSCR configuration. It also adds new idle states
> stop0_lite, stop1_lite and stop2_lite which are no state loss versions
> of stop0, stop1 and stop2 respectively. The lite variant has EC and
> ESL bits of PSSCR set to 0. The thread entering a lite variant of stop
> state will not lose any state and will wakeup at next instruction
> following stop if MSR.EE=0 or at the corresponding interrupt handler
> if MSR.EE=1. This will reduce the exit latency of the idle state and
> hardware will not allocate the thread resources to other threads while
> in power saving mode.
> Signed-off-by: Shilpasri G Bhat <shilpa.bhat at linux.vnet.ibm.com>
> ---
> Changes from v1:
> - Added PSSCR register value and mask for each idle state
> - Modified commit message and log
>  hw/slw.c           | 92 +++++++++++++++++++++++++++++++++++++++++++++---------
>  include/opal-api.h | 15 +++++++++
>  2 files changed, 93 insertions(+), 14 deletions(-)

Thanks! Merged to master as of 739063fb706f987df2a766a981abc75053244044

Stewart Smith
OPAL Architect, IBM.

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