[Skiboot] [PATCH] phb4: Trivial whitespace fixes
Russell Currey
ruscur at russell.cc
Fri Aug 5 13:46:26 AEST 2016
Signed-off-by: Russell Currey <ruscur at russell.cc>
---
hw/phb4.c | 32 ++++++++++++++++----------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/hw/phb4.c b/hw/phb4.c
index 734146c..3660fe4 100644
--- a/hw/phb4.c
+++ b/hw/phb4.c
@@ -365,7 +365,7 @@ static int64_t phb4_pcicfg_read(struct phb4 *p, uint32_t bdfn,
#define PHB4_PCI_CFG_READ(size, type) \
static int64_t phb4_pcicfg_read##size(struct phb *phb, uint32_t bdfn, \
- uint32_t offset, type *data) \
+ uint32_t offset, type *data) \
{ \
struct phb4 *p = phb_to_phb4(phb); \
\
@@ -440,12 +440,12 @@ static int64_t phb4_pcicfg_write(struct phb4 *p, uint32_t bdfn,
}
#endif
}
- return OPAL_SUCCESS;
+ return OPAL_SUCCESS;
}
#define PHB4_PCI_CFG_WRITE(size, type) \
static int64_t phb4_pcicfg_write##size(struct phb *phb, uint32_t bdfn, \
- uint32_t offset, type data) \
+ uint32_t offset, type data) \
{ \
struct phb4 *p = phb_to_phb4(phb); \
\
@@ -1534,7 +1534,7 @@ static void phb4_read_phb_status(struct phb4 *p,
static int64_t phb4_set_pe(struct phb *phb,
uint64_t pe_num,
- uint64_t bdfn,
+ uint64_t bdfn,
uint8_t bcompare,
uint8_t dcompare,
uint8_t fcompare,
@@ -1951,10 +1951,10 @@ static int64_t phb4_pfreset(struct pci_slot *slot)
/* CAPP FPGA requires 1s to flash before polling link */
return pci_slot_set_sm_timeout(slot, secs_to_tb(1));
case PHB4_SLOT_PFRESET_DEASSERT_DELAY:
-#if 0 /* PHB3 does a Hreset here. It's unnecessary I think and it's
- causing problems with the simulator croc model so don't do
- it until I figure out Gavin's reasons
- */
+#if 0 /* PHB3 does a Hreset here. It's unnecessary I think and it's
+ * causing problems with the simulator croc model so don't do
+ * it until I figure out Gavin's reasons
+ */
pci_slot_set_state(slot, PHB4_SLOT_HRESET_START);
return slot->ops.hreset(slot);
#else
@@ -2172,10 +2172,10 @@ static int64_t phb4_eeh_freeze_clear(struct phb *phb, uint64_t pe_number,
}
static int64_t phb4_eeh_freeze_set(struct phb *phb, uint64_t pe_number,
- uint64_t eeh_action_token)
+ uint64_t eeh_action_token)
{
- struct phb4 *p = phb_to_phb4(phb);
- uint64_t data;
+ struct phb4 *p = phb_to_phb4(phb);
+ uint64_t data;
if (p->state == PHB4_STATE_BROKEN)
return OPAL_HARDWARE;
@@ -2256,7 +2256,7 @@ static int64_t phb4_eeh_next_error(struct phb *phb,
break;
}
}
- }
+ }
/* Mapping errors */
if (phb4_err_pending(p)) {
@@ -2312,7 +2312,7 @@ static int64_t phb4_eeh_next_error(struct phb *phb,
phb4_set_err_pending(p, false);
}
- break;
+ break;
case PHB4_ERR_CLASS_INF:
*pci_error_type = OPAL_EEH_PHB_ERROR;
*severity = OPAL_EEH_SEV_INF;
@@ -2534,7 +2534,7 @@ static bool phb4_init_rc_cfg(struct phb4 *p)
PCIECAP_AER_UE_POISON_TLP |
PCIECAP_AER_UE_COMPL_TIMEOUT |
PCIECAP_AER_UE_COMPL_ABORT);
-
+
/* Clear all CE status */
phb4_pcicfg_write32(&p->phb, 0, aercap + PCIECAP_AER_CE_STATUS,
0xffffffff);
@@ -2718,7 +2718,7 @@ static void phb4_init_hw(struct phb4 *p, bool first_init)
phb4_init_errors(p);
/* Init_121..122 : Wait for link
- * NOTE: At this point the spec waits for the link to come up. We
+ * NOTE: At this point the spec waits for the link to come up. We
* don't bother as we are doing a PERST soon.
*/
@@ -2726,7 +2726,7 @@ static void phb4_init_hw(struct phb4 *p, bool first_init)
// XXX FIXME learn CAPI :-(
/* Init_124 : Setup PCI command/status on root complex
- * I don't know why the spec does this now and not earlier, so
+ * I don't know why the spec does this now and not earlier, so
* to be sure to get it right we might want to move it to the freset
* state machine, though the generic PCI layer will probably do
* this anyway (ie, enable MEM, etc... in the RC)
--
2.9.2
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