[Skiboot] [PATCH] hw/phb3: Flush cache line after updating P/Q bits

[Stewart Smith]

Benjamin Herrenschmidt <benh at kernel.crashing.org> writes:
> When doing an MSI EOI, we update the P and Q bits in the IVE. That causes
> the corresponding cache line to be dirty in the L3 which will cause a
> subsequent update by the PHB (upon recieving the next MSI) to get a few
> retries until it gets flushed.
>
> We can improve the situation (and thus performance) by doing a dcbf
> instruction to force a flush of the update we do in SW.
>
> Signed-off-by: Benjamin Herrenschmidt <benh at kernel.crashing.org>

For some bizarre reason git (and /usr/bin/patch) told me the patch was
corrupt, but never mind - applied by hand.

Merged to update-2.1.1.1 as of 53def38
Merged to stable as of b96a20e
merged to master as of 1cec33c