[Skiboot] [PATCH 19/36] sparse: Fix many constant is too big warninsg in p7ioc code
Stewart Smith
stewart at linux.vnet.ibm.com
Tue Nov 10 15:18:13 AEDT 2015
e.g.
hw/p7ioc.c:238:41: warning: constant 0x0002000000000000 is so big it is long
Signed-off-by: Stewart Smith <stewart at linux.vnet.ibm.com>
---
hw/p7ioc-inits.c | 590 +++++++++++++++++++++++++++----------------------------
hw/p7ioc-phb.c | 180 ++++++++---------
hw/p7ioc.c | 54 ++---
3 files changed, 412 insertions(+), 412 deletions(-)
diff --git a/hw/p7ioc-inits.c b/hw/p7ioc-inits.c
index dc5c3703b45d..0d50694a2dd4 100644
--- a/hw/p7ioc-inits.c
+++ b/hw/p7ioc-inits.c
@@ -56,9 +56,9 @@ static void p7ioc_init_BI(struct p7ioc *ioc)
printf("P7IOC: -> Configured for P7+\n");
/* Chicken switches */
- REGW(0x3c00d8, 0x0004000000000600);
+ REGW(0x3c00d8, 0x0004000000000600UL);
/* GX config */
- REGW(0x3c00a0, 0x9F8929BE00880085);
+ REGW(0x3c00a0, 0x9F8929BE00880085UL);
} else {
printf("P7IOC: -> Configured for P7\n");
@@ -68,9 +68,9 @@ static void p7ioc_init_BI(struct p7ioc *ioc)
* xscom ?
*/
/* Chicken switches */
- REGW(0x3c00d8, 0x00040000000004C0);
+ REGW(0x3c00d8, 0x00040000000004C0UL);
/* GX config */
- REGW(0x3c00a0, 0x9C8929BE00880085);
+ REGW(0x3c00a0, 0x9C8929BE00880085UL);
}
/*
@@ -81,160 +81,160 @@ static void p7ioc_init_BI(struct p7ioc *ioc)
time_wait_ms(100);
/* Init_3: Upbound Credit Config */
- REGW(0x3c00c8, 0x0303060403030000);
+ REGW(0x3c00c8, 0x0303060403030000UL);
/* Init_4: Credit Init Timer */
- REGW(0x3c00e8, 0x00000000000000FF);
+ REGW(0x3c00e8, 0x00000000000000FFUL);
/* Init_4.1: BI Ack Timing */
- REGW(0x3c00e8, 0x0000FC0000000000);
+ REGW(0x3c00e8, 0x0000FC0000000000UL);
/* Init_5: Ordering Override 0*/
- REGW(0x3c0200, 0x0000000000000000);
+ REGW(0x3c0200, 0x0000000000000000UL);
/* Init_6: Ordering Override 1*/
- REGW(0x3c0208, 0x0000000000000000);
+ REGW(0x3c0208, 0x0000000000000000UL);
/*** Downbound TTYPE table ***/
/* Init_7: Enable sequence / speculation for CI Loads */
- REGW(0x3c00a8, 0x0000000000000004);
+ REGW(0x3c00a8, 0x0000000000000004UL);
/* Init_8: */
- REGW(0x3c00b0, 0x700800C000000000);
+ REGW(0x3c00b0, 0x700800C000000000UL);
/* Init_9: Enable sequence / speculation for CI Stores */
- REGW(0x3c00a8, 0x0000000000000005);
+ REGW(0x3c00a8, 0x0000000000000005UL);
/* Init_10: */
- REGW(0x3c00b0, 0x704820C000000000);
+ REGW(0x3c00b0, 0x704820C000000000UL);
/* Init_11: Enable speculation for EOI */
- REGW(0x3c00a8, 0x000000000000001B);
+ REGW(0x3c00a8, 0x000000000000001BUL);
/* Init_12: */
- REGW(0x3c00b0, 0x3590204000000000);
+ REGW(0x3c00b0, 0x3590204000000000UL);
/* Init_13: ENable speculation for DMA Rd Responses */
- REGW(0x3c00a8, 0x0000000000000020);
+ REGW(0x3c00a8, 0x0000000000000020UL);
/* Init_14: */
- REGW(0x3c00b0, 0x1103C4C000000000);
+ REGW(0x3c00b0, 0x1103C4C000000000UL);
/* Init_15: Enable sequence for DMA RWNITC */
- REGW(0x3c00a8, 0x0000000000000001);
+ REGW(0x3c00a8, 0x0000000000000001UL);
/* Init_16: */
- REGW(0x3c00b0, 0xC000000000000000);
+ REGW(0x3c00b0, 0xC000000000000000UL);
/* Init_17: Enable sequence for IOKill */
- REGW(0x3c00a8, 0x0000000000000009);
+ REGW(0x3c00a8, 0x0000000000000009UL);
/* Init_18: */
- REGW(0x3c00b0, 0x4208210000000000);
+ REGW(0x3c00b0, 0x4208210000000000UL);
/* Init_19: Enable sequence for IOKill */
- REGW(0x3c00a8, 0x000000000000000A);
+ REGW(0x3c00a8, 0x000000000000000AUL);
/* Init_20: */
- REGW(0x3c00b0, 0x4200210000000000);
+ REGW(0x3c00b0, 0x4200210000000000UL);
/* Init_21: Enable sequence for FMTC CI Store w/Kill */
- REGW(0x3c00a8, 0x0000000000000021);
+ REGW(0x3c00a8, 0x0000000000000021UL);
/*** Timer controls ***/
/* Init_22: */
- REGW(0x3c00b0, 0x4200300000000000);
+ REGW(0x3c00b0, 0x4200300000000000UL);
/* Init_23: Dnbound timer mask */
- REGW(0x3c0190, 0x0040000000000000);
+ REGW(0x3c0190, 0x0040000000000000UL);
/* Init_24: Upbound timer mask 0 */
- REGW(0x3c0180, 0x0010001000100010);
+ REGW(0x3c0180, 0x0010001000100010UL);
/* Init_25: Upbound timer mask 1 */
- REGW(0x3c0188, 0x0010000000000000);
+ REGW(0x3c0188, 0x0010000000000000UL);
/* Init_26: Credit sync check config */
- REGW(0x3c00f0, 0xC102000000000000);
+ REGW(0x3c00f0, 0xC102000000000000UL);
/*** Setup trace ***/
/* Init_27: DBG stop trace */
- REGW(0x3c0410, 0x4000000000000000);
+ REGW(0x3c0410, 0x4000000000000000UL);
/* Init_28: DBG control */
- REGW(0x3c0400, 0x0000000000000000);
+ REGW(0x3c0400, 0x0000000000000000UL);
/* Init_29: DBG Mode */
- REGW(0x3c0408, 0xA0000000F0CC3300);
+ REGW(0x3c0408, 0xA0000000F0CC3300UL);
/* Init_29a: DBG C0 (Stop on Error) */
- REGW(0x3c0418, 0xF4F00FFF00000000);
+ REGW(0x3c0418, 0xF4F00FFF00000000UL);
/* Init_30: DBG pre-mux select */
- REGW(0x3c0478, 0x0023000000000000);
+ REGW(0x3c0478, 0x0023000000000000UL);
/* Init_31: CA0 mode */
- REGW(0x3c04b0, 0x8000000000000000);
+ REGW(0x3c04b0, 0x8000000000000000UL);
/* Init_32: CA0 Compression 0 */
- REGW(0x3c04b8, 0x0000000000000000);
+ REGW(0x3c04b8, 0x0000000000000000UL);
/* Init_33: CA0 Compression 1 */
- REGW(0x3c04c0, 0x0000000000000000);
+ REGW(0x3c04c0, 0x0000000000000000UL);
/* Init_34: CA0 Pattern A march (cmd1 selected val) */
- REGW(0x3c0480, 0x008000007FFFFF00);
+ REGW(0x3c0480, 0x008000007FFFFF00UL);
/* Init_35: CA0 Trigger 0 definition (pattern A) */
- REGW(0x3c04a0, 0x8000000000000000);
+ REGW(0x3c04a0, 0x8000000000000000UL);
/* Init_36: CA1 mode */
- REGW(0x3c0530, 0x8000000000000000);
+ REGW(0x3c0530, 0x8000000000000000UL);
/* Init_37: CA1 Compression 0 */
- REGW(0x3c0538, 0x0000000000000000);
+ REGW(0x3c0538, 0x0000000000000000UL);
/* Init_38: CA1 Compression 1 */
- REGW(0x3c0540, 0x0000000000000000);
+ REGW(0x3c0540, 0x0000000000000000UL);
/* Init_39: CA2 mode */
- REGW(0x3c05b0, 0x8000000000000000);
+ REGW(0x3c05b0, 0x8000000000000000UL);
/* Init_40: CA2 Compression 0 */
- REGW(0x3c05b8, 0x0000000000000000);
+ REGW(0x3c05b8, 0x0000000000000000UL);
/* Init_41: CA2 Compression 1 */
- REGW(0x3c05c0, 0x0000000000000000);
+ REGW(0x3c05c0, 0x0000000000000000UL);
/* Init_42: CA3 Mode */
- REGW(0x3c0630, 0x8000000000000000);
+ REGW(0x3c0630, 0x8000000000000000UL);
/* Init_43: CA3 Compression 0 */
- REGW(0x3c0638, 0x0000000000000000);
+ REGW(0x3c0638, 0x0000000000000000UL);
/* Init_44: CA3 Compression 1 */
- REGW(0x3c0640, 0x0000000000000000);
+ REGW(0x3c0640, 0x0000000000000000UL);
/* Init_45: CA3 Pattern A match (AIB val) */
- REGW(0x3c0600, 0x80000100FFFEFF00);
+ REGW(0x3c0600, 0x80000100FFFEFF00UL);
/* Init_46: CA3 Trigger 0 definition (pattern A) */
- REGW(0x3c0620, 0x8000000000000000);
+ REGW(0x3c0620, 0x8000000000000000UL);
/* Init_47: DBG unfreeze trace */
- REGW(0x3c0410, 0x1000000000000000);
+ REGW(0x3c0410, 0x1000000000000000UL);
/* Init_48: DBG start trace */
- REGW(0x3c0410, 0x8000000000000000);
+ REGW(0x3c0410, 0x8000000000000000UL);
/*** AIB Port Config ***/
/* Init_49: AIB Port Information */
- REGW(0x3c00d0, 0x0888888800000000);
+ REGW(0x3c00d0, 0x0888888800000000UL);
/* Init_50: Port Ordering controls */
- REGW(0x3c0200, 0x0000000000000000);
+ REGW(0x3c0200, 0x0000000000000000UL);
/*** LEMs (need to match recov. tables) ***/
/* Init_51: Clear upbound LEM */
- REGW(0x3c0000, 0x0000000000000000);
+ REGW(0x3c0000, 0x0000000000000000UL);
/* Init_52: Clear upbound WOF */
- REGW(0x3c0040, 0x0000000000000000);
+ REGW(0x3c0040, 0x0000000000000000UL);
/* Init_53: Clear Dnbound LEM */
- REGW(0x3c0050, 0x0000000000000000);
+ REGW(0x3c0050, 0x0000000000000000UL);
/* Init_54: Clear Dnbound WOF */
- REGW(0x3c0090, 0x0000000000000000);
+ REGW(0x3c0090, 0x0000000000000000UL);
/* Init_55: Clear Fences */
- REGW(0x3c0130, 0x0000000000000000);
+ REGW(0x3c0130, 0x0000000000000000UL);
/* Init_56: Clear Erpt latches */
- REGW(0x3c0148, 0x0080000000000000);
+ REGW(0x3c0148, 0x0080000000000000UL);
/* Init_57: Set Upbound LEM Action0 */
- REGW(0x3c0030, 0x0800000000800000);
+ REGW(0x3c0030, 0x0800000000800000UL);
/* Init_58: Set Upbound LEN Action1 */
- REGW(0x3c0038, 0x0000000000000000);
+ REGW(0x3c0038, 0x0000000000000000UL);
/* Init_59: Set Upbound LEM Mask (AND write) */
- REGW(0x3c0020, 0x0800000000000000);
+ REGW(0x3c0020, 0x0800000000000000UL);
/* Init_60: Set Dnbound LEM Action0 */
- REGW(0x3c0080, 0x2000080CA07FFF40);
+ REGW(0x3c0080, 0x2000080CA07FFF40UL);
/* Init_61: Set Dnbound LEM Action1 */
- REGW(0x3c0088, 0x0000000000000000);
+ REGW(0x3c0088, 0x0000000000000000UL);
/* Init_62: Set Dnbound LEM Mask (AND write) */
- REGW(0x3c0070, 0x00000800200FFE00);
+ REGW(0x3c0070, 0x00000800200FFE00UL);
/*** Setup Fences (need to match recov. tables) ***/
/* Init_63: Set Upbound Damage Control 0 (GX Err) */
- REGW(0x3c0100, 0xF7FFFFFFFF7FFFFF);
+ REGW(0x3c0100, 0xF7FFFFFFFF7FFFFFUL);
/* Init_64: Set Upbound Damage Control 1 (AIB Fence) */
- REGW(0x3c0108, 0xF7FFFFFFFF7FFFFF);
+ REGW(0x3c0108, 0xF7FFFFFFFF7FFFFFUL);
/* Init_65: Set Upbound Damage Control 2 (Drop Pkt) */
- REGW(0x3c0110, 0x0010054000000000);
+ REGW(0x3c0110, 0x0010054000000000UL);
/* Init_66: Set Dnbound Damage Control 0 (GX Err) */
- REGW(0x3c0118, 0xDFFFF7F35F8000BF);
+ REGW(0x3c0118, 0xDFFFF7F35F8000BFUL);
/* Init_67: Set Dnbound Damage Control 1 (AIB Fence) */
- REGW(0x3c0120, 0xDFFFF7F35F8000BF);
+ REGW(0x3c0120, 0xDFFFF7F35F8000BFUL);
/* Init_68: Set Dnbound Damage Control 2 (Drop Pkt) */
- REGW(0x3c0128, 0x0000000C00000000);
+ REGW(0x3c0128, 0x0000000C00000000UL);
}
static void p7ioc_init_MISC_HSS(struct p7ioc *ioc)
@@ -255,11 +255,11 @@ static void p7ioc_init_MISC_HSS(struct p7ioc *ioc)
continue;
/* Init_1: HSSn CTL2 */
- REGW(regbase + P7IOC_HSSn_CTL2_OFFSET, 0xFFFF6DB6DB000000);
+ REGW(regbase + P7IOC_HSSn_CTL2_OFFSET, 0xFFFF6DB6DB000000UL);
/* Init_2: HSSn CTL3 */
- REGW(regbase + P7IOC_HSSn_CTL3_OFFSET, 0x1130000320000000);
+ REGW(regbase + P7IOC_HSSn_CTL3_OFFSET, 0x1130000320000000UL);
/* Init_3: HSSn CTL8 */
- REGW(regbase + P7IOC_HSSn_CTL8_OFFSET, 0xDDDDDDDD00000000);
+ REGW(regbase + P7IOC_HSSn_CTL8_OFFSET, 0xDDDDDDDD00000000UL);
#if 0 /* All these remain set to the values configured by the FSP */
/* Init_4: HSSn CTL9 */
@@ -316,27 +316,27 @@ static void p7ioc_init_RGC(struct p7ioc *ioc)
/*** Set LEM regs (needs to match recov. code) */
/* Init_3: LEM FIR Accumulator */
- REGW(0x3e1e00, 0x0000000000000000);
+ REGW(0x3e1e00, 0x0000000000000000UL);
/* Init_4: LEM Action 0 */
- REGW(0x3e1e30, 0x0FFF791F0B030000);
+ REGW(0x3e1e30, 0x0FFF791F0B030000UL);
/* Init_5: LEN Action 1 */
- REGW(0x3e1e38, 0x0000000000000000);
+ REGW(0x3e1e38, 0x0000000000000000UL);
/* Init_6: LEM WOF */
- REGW(0x3e1e40, 0x0000000000000000);
+ REGW(0x3e1e40, 0x0000000000000000UL);
/* Init_7: LEM Mask Reg (AND write) */
- REGW(0x3e1e20, 0x0FFF001F03030000);
+ REGW(0x3e1e20, 0x0FFF001F03030000UL);
/*** Set GEM regs (masks still on, no irpts can occur yet) ***/
/* Init_8: GEM XFIR */
- REGW(0x3e0008, 0x0000000000000000);
+ REGW(0x3e0008, 0x0000000000000000UL);
/* Init_9: GEM WOF */
- REGW(0x3e0028, 0x0000000000000000);
+ REGW(0x3e0028, 0x0000000000000000UL);
/*** Set Damage Controls (needs to match recov.) ***/
/* Init_10: LDCP */
- REGW(0x3e1c18, 0xF00086C0B4FCFFFF);
+ REGW(0x3e1c18, 0xF00086C0B4FCFFFFUL);
/*** Read status (optional) ***/
@@ -347,15 +347,15 @@ static void p7ioc_init_RGC(struct p7ioc *ioc)
/*** Set running configuration **/
/* Init_12: Configuration reg (modes, values, timers) */
- REGW(0x3e1c08, 0x10000077CE100000);
+ REGW(0x3e1c08, 0x10000077CE100000UL);
/* Init_13: Cmd/Dat Crd Allocation */
- REGW(0x3e1c20, 0x00000103000700FF);
+ REGW(0x3e1c20, 0x00000103000700FFUL);
/* Init_14: GP reg - disable errs, wrap, stop_trc */
- REGW(0x3e1018, 0x0000000000000000);
+ REGW(0x3e1018, 0x0000000000000000UL);
/* Init_15: Configuration reg (start init timers) */
cfg = REGR(0x3e1c08);
- REGW(0x3e1c08, cfg | 0x00003f0000000000);
+ REGW(0x3e1c08, cfg | 0x00003f0000000000UL);
/*** Setup interrupts ***/
@@ -386,29 +386,29 @@ static void p7ioc_init_RGC(struct p7ioc *ioc)
//REGR(0x3e1840, 0x0000000000000000);
/* Init_18: IODA Table Addr: Select IST*/
- REGW(0x3e1820, 0x8001000000000000);
+ REGW(0x3e1820, 0x8001000000000000UL);
/* Init_19: IODA Table Data: IRPT 0 */
- REGW(0x3e1830, 0x0000000000000000);
+ REGW(0x3e1830, 0x0000000000000000UL);
/* Init_20: IODA Table Data: IRPT 1 */
- REGW(0x3e1830, 0x0000000000000000);
+ REGW(0x3e1830, 0x0000000000000000UL);
/* Init_21: IODA Table Addr: Select HRT */
- REGW(0x3e1820, 0x8000000000000000);
+ REGW(0x3e1820, 0x8000000000000000UL);
/* Init_22: IODA Table Data: HRT
*
* XXX Figure out what this actually is and what value should
* we use. For now, do like BML and use 0
*/
for (i = 0; i < 4; i++)
- REGW(0x3e1830, 0x0000000000000000);
+ REGW(0x3e1830, 0x0000000000000000UL);
/* Init_23: IODA Table Addr: select XIVT */
- REGW(0x3e1820, 0x8002000000000000);
+ REGW(0x3e1820, 0x8002000000000000UL);
/* Init_24: IODA Table Data: Mask all interrupts */
for (i = 0; i < 16; i++)
- REGW(0x3e1830, 0x000000ff00000000);
+ REGW(0x3e1830, 0x000000ff00000000UL);
/* Init_25: Clear table lock if any was stale */
- REGW(0x3e1840, 0x0000000000000000);
+ REGW(0x3e1840, 0x0000000000000000UL);
/* Init_32..37: Set the PHB AIB addresses. We configure those
* to the values recommended in the p7IOC doc.
@@ -536,8 +536,8 @@ static void p7ioc_init_ci_routing(struct p7ioc *ioc)
REGW(P7IOC_CI_RMATC_REG(i), rmatch[i]);
/* Init_225: CI Match 47 (Configure RGC catch all) */
- REGW(P7IOC_CI_RMASK_REG(47), 0x0000000000000000);
- REGW(P7IOC_CI_RMATC_REG(47), 0x4000800000000000);
+ REGW(P7IOC_CI_RMASK_REG(47), 0x0000000000000000UL);
+ REGW(P7IOC_CI_RMATC_REG(47), 0x4000800000000000UL);
#ifdef DUMP_CI_ROUTING
printf("P7IOC: CI Routing table:\n");
@@ -560,189 +560,189 @@ static void p7ioc_init_CI(struct p7ioc *ioc)
*/
/* Init_1: CI Port 0 Configuration */
- REGW(0x3d0000, 0x420000C0073F0002);
+ REGW(0x3d0000, 0x420000C0073F0002UL);
/* Init_2: CI Port 0 Configuration */
- REGW(0x3d0000, 0x020000C0073F0002);
+ REGW(0x3d0000, 0x020000C0073F0002UL);
/* Init_3: CI Port 1 Configuration */
- REGW(0x3d1000, 0x42000FCF07200002);
+ REGW(0x3d1000, 0x42000FCF07200002UL);
/* Init_4: CI Port 1 Configuration */
- REGW(0x3d1000, 0x02000FCF07200002);
+ REGW(0x3d1000, 0x02000FCF07200002UL);
/* Init_5: CI Port 2 Configuration */
- REGW(0x3d2000, 0x420000C307200002);
+ REGW(0x3d2000, 0x420000C307200002UL);
/* Init_6: CI Port 2 Configuration */
- REGW(0x3d2000, 0x020000C307200002);
+ REGW(0x3d2000, 0x020000C307200002UL);
/* Init_7: CI Port 3 Configuration */
- REGW(0x3d3000, 0x420000C307200002);
+ REGW(0x3d3000, 0x420000C307200002UL);
/* Init_8: CI Port 3 Configuration */
- REGW(0x3d3000, 0x020000C307200002);
+ REGW(0x3d3000, 0x020000C307200002UL);
/* Init_9: CI Port 4 Configuration */
- REGW(0x3d4000, 0x420000C307200002);
+ REGW(0x3d4000, 0x420000C307200002UL);
/* Init_10: CI Port 4 Configuration */
- REGW(0x3d4000, 0x020000C307200002);
+ REGW(0x3d4000, 0x020000C307200002UL);
/* Init_11: CI Port 5 Configuration */
- REGW(0x3d5000, 0x420000C307200002);
+ REGW(0x3d5000, 0x420000C307200002UL);
/* Init_12: CI Port 5 Configuration */
- REGW(0x3d5000, 0x020000C307200002);
+ REGW(0x3d5000, 0x020000C307200002UL);
/* Init_13: CI Port 6 Configuration */
- REGW(0x3d6000, 0x420000C307200002);
+ REGW(0x3d6000, 0x420000C307200002UL);
/* Init_14: CI Port 6 Configuration */
- REGW(0x3d6000, 0x020000C307200002);
+ REGW(0x3d6000, 0x020000C307200002UL);
/* Init_15: CI Port 7 Configuration */
- REGW(0x3d7000, 0x420000C307200002);
+ REGW(0x3d7000, 0x420000C307200002UL);
/* Init_16: CI Port 7 Configuration */
- REGW(0x3d7000, 0x020000C307200002);
+ REGW(0x3d7000, 0x020000C307200002UL);
/*** Set LEM regs (need to match recov.) ***/
/* Init_17: CI Port 0 LEM FIR Accumulator */
- REGW(0x3d0200, 0x0000000000000000);
+ REGW(0x3d0200, 0x0000000000000000UL);
/* Init_18: CI Port 0 LEM Action 0 */
- REGW(0x3d0230, 0x0A00000000000000);
+ REGW(0x3d0230, 0x0A00000000000000UL);
/* Init_19: CI Port 0 LEM Action 1 */
- REGW(0x3d0238, 0x0000000000000000);
+ REGW(0x3d0238, 0x0000000000000000UL);
/* Init_20: CI Port 0 LEM WOF */
- REGW(0x3d0240, 0x0000000000000000);
+ REGW(0x3d0240, 0x0000000000000000UL);
/* Init_21: CI Port 0 LEM Mask (AND write) */
- REGW(0x3d0220, 0x0200000000000000);
+ REGW(0x3d0220, 0x0200000000000000UL);
/* Init_22: CI Port 1 LEM FIR Accumularor */
- REGW(0x3d1200, 0x0000000000000000);
+ REGW(0x3d1200, 0x0000000000000000UL);
/* Init_23: CI Port 1 LEM Action 0 */
- REGW(0x3d1230, 0x0000000000000000);
+ REGW(0x3d1230, 0x0000000000000000UL);
/* Init_24: CI Port 1 LEM Action 1 */
- REGW(0x3d1238, 0x0000000000000000);
+ REGW(0x3d1238, 0x0000000000000000UL);
/* Init_25: CI Port 1 LEM WOF */
- REGW(0x3d1240, 0x0000000000000000);
+ REGW(0x3d1240, 0x0000000000000000UL);
/* Init_26: CI Port 1 LEM Mask (AND write) */
- REGW(0x3d1220, 0x0000000000000000);
+ REGW(0x3d1220, 0x0000000000000000UL);
/* Init_27: CI Port 2 LEM FIR Accumulator */
- REGW(0x3d2200, 0x0000000000000000);
+ REGW(0x3d2200, 0x0000000000000000UL);
/* Init_28: CI Port 2 LEM Action 0 */
- REGW(0x3d2230, 0xA4F4000000000000);
+ REGW(0x3d2230, 0xA4F4000000000000UL);
/* Init_29: CI Port 2 LEM Action 1 */
- REGW(0x3d2238, 0x0000000000000000);
+ REGW(0x3d2238, 0x0000000000000000UL);
/* Init_30: CI Port 2 LEM WOF */
- REGW(0x3d2240, 0x0000000000000000);
+ REGW(0x3d2240, 0x0000000000000000UL);
/* Init_31: CI Port 2 LEM Mask (AND write) */
- REGW(0x3d2220, 0x0000000000000000);
+ REGW(0x3d2220, 0x0000000000000000UL);
/* Init_32: CI Port 3 LEM FIR Accumulator */
- REGW(0x3d3200, 0x0000000000000000);
+ REGW(0x3d3200, 0x0000000000000000UL);
/* Init_33: CI Port 3 LEM Action 0 */
- REGW(0x3d3230, 0xA4F4000000000000);
+ REGW(0x3d3230, 0xA4F4000000000000UL);
/* Init_34: CI Port 3 LEM Action 1 */
- REGW(0x3d3238, 0x0000000000000000);
+ REGW(0x3d3238, 0x0000000000000000UL);
/* Init_35: CI Port 3 LEM WOF */
- REGW(0x3d3240, 0x0000000000000000);
+ REGW(0x3d3240, 0x0000000000000000UL);
/* Init_36: CI Port 3 LEM Mask (AND write) */
- REGW(0x3d3220, 0x0000000000000000);
+ REGW(0x3d3220, 0x0000000000000000UL);
/* Init_37: CI Port 4 LEM FIR Accumulator */
- REGW(0x3d4200, 0x0000000000000000);
+ REGW(0x3d4200, 0x0000000000000000UL);
/* Init_38: CI Port 4 Action 0 */
- REGW(0x3d4230, 0xA4F4000000000000);
+ REGW(0x3d4230, 0xA4F4000000000000UL);
/* Init_39: CI Port 4 Action 1 */
- REGW(0x3d4238, 0x0000000000000000);
+ REGW(0x3d4238, 0x0000000000000000UL);
/* Init_40: CI Port 4 WOF */
- REGW(0x3d4240, 0x0000000000000000);
+ REGW(0x3d4240, 0x0000000000000000UL);
/* Init_41: CI Port 4 Mask (AND write) */
- REGW(0x3d4220, 0x0000000000000000);
+ REGW(0x3d4220, 0x0000000000000000UL);
/* Init_42: CI Port 5 LEM FIR Accumulator */
- REGW(0x3d5200, 0x0000000000000000);
+ REGW(0x3d5200, 0x0000000000000000UL);
/* Init_43: CI Port 5 Action 0 */
- REGW(0x3d5230, 0xA4F4000000000000);
+ REGW(0x3d5230, 0xA4F4000000000000UL);
/* Init_44: CI Port 5 Action 1 */
- REGW(0x3d5238, 0x0000000000000000);
+ REGW(0x3d5238, 0x0000000000000000UL);
/* Init_45: CI Port 4 WOF */
- REGW(0x3d5240, 0x0000000000000000);
+ REGW(0x3d5240, 0x0000000000000000UL);
/* Init_46: CI Port 5 Mask (AND write) */
- REGW(0x3d5220, 0x0000000000000000);
+ REGW(0x3d5220, 0x0000000000000000UL);
/* Init_47: CI Port 6 LEM FIR Accumulator */
- REGW(0x3d6200, 0x0000000000000000);
+ REGW(0x3d6200, 0x0000000000000000UL);
/* Init_48: CI Port 6 Action 0 */
- REGW(0x3d6230, 0xA4F4000000000000);
+ REGW(0x3d6230, 0xA4F4000000000000UL);
/* Init_49: CI Port 6 Action 1 */
- REGW(0x3d6238, 0x0000000000000000);
+ REGW(0x3d6238, 0x0000000000000000UL);
/* Init_50: CI Port 6 WOF */
- REGW(0x3d6240, 0x0000000000000000);
+ REGW(0x3d6240, 0x0000000000000000UL);
/* Init_51: CI Port 6 Mask (AND write) */
- REGW(0x3d6220, 0x0000000000000000);
+ REGW(0x3d6220, 0x0000000000000000UL);
/* Init_52: CI Port 7 LEM FIR Accumulator */
- REGW(0x3d7200, 0x0000000000000000);
+ REGW(0x3d7200, 0x0000000000000000UL);
/* Init_53: CI Port 7 Action 0 */
- REGW(0x3d7230, 0xA4F4000000000000);
+ REGW(0x3d7230, 0xA4F4000000000000UL);
/* Init_54: CI Port 7 Action 1 */
- REGW(0x3d7238, 0x0000000000000000);
+ REGW(0x3d7238, 0x0000000000000000UL);
/* Init_55: CI Port 7 WOF */
- REGW(0x3d7240, 0x0000000000000000);
+ REGW(0x3d7240, 0x0000000000000000UL);
/* Init_56: CI Port 7 Mask (AND write) */
- REGW(0x3d7220, 0x0000000000000000);
+ REGW(0x3d7220, 0x0000000000000000UL);
/*** Set Damage Controls (need match recov.) ***/
/* Init_57: CI Port 0 LDCP*/
- REGW(0x3d0010, 0x421A0000000075FF);
+ REGW(0x3d0010, 0x421A0000000075FFUL);
/* Init_58: CI Port 1 LDCP */
- REGW(0x3d1010, 0x421A000000007FFF);
+ REGW(0x3d1010, 0x421A000000007FFFUL);
/* Init_59: CI Port 2 LDCP */
- REGW(0x3d2010, 0x421A24F400005B0B);
+ REGW(0x3d2010, 0x421A24F400005B0BUL);
/* Init_60: CI Port 3 LDCP */
- REGW(0x3d3010, 0x421A24F400005B0B);
+ REGW(0x3d3010, 0x421A24F400005B0BUL);
/* Init_61: CI Port 4 LDCP */
- REGW(0x3d4010, 0x421A24F400005B0B);
+ REGW(0x3d4010, 0x421A24F400005B0BUL);
/* Init_62: CI Port 5 LDCP */
- REGW(0x3d5010, 0x421A24F400005B0B);
+ REGW(0x3d5010, 0x421A24F400005B0BUL);
/* Init_63: CI Port 6 LDCP */
- REGW(0x3d6010, 0x421A24F400005B0B);
+ REGW(0x3d6010, 0x421A24F400005B0BUL);
/* Init_64: CI Port 7 LDCP */
- REGW(0x3d7010, 0x421A24F400005B0B);
+ REGW(0x3d7010, 0x421A24F400005B0BUL);
/*** Setup Trace 0 ***/
/* Init_65: CI Trc 0 DBG - Run/Status (stop trace) */
- REGW(0x3d0810, 0x5000000000000000);
+ REGW(0x3d0810, 0x5000000000000000UL);
/* Init_66: CI Trc 0 DBG - Mode (not cross trig CA's) */
- REGW(0x3d0808, 0xB0000000F0000000);
+ REGW(0x3d0808, 0xB0000000F0000000UL);
/* Init_66a: CI Trc 0 DBG - C0 (stop on error) */
- REGW(0x3d0818, 0xF4F00FFF00000000);
+ REGW(0x3d0818, 0xF4F00FFF00000000UL);
/* Init_67: CI Trc 0 DBG - Select (port 0 mode 2) */
- REGW(0x3d0878, 0x0002000000000000);
+ REGW(0x3d0878, 0x0002000000000000UL);
/* Init_68: CI Trc 0 CA0 - Pattern A (RX cmd val) */
- REGW(0x3d0880, 0xC0200000DFFFFF00);
+ REGW(0x3d0880, 0xC0200000DFFFFF00UL);
/* Init_69: CI Trc 0 CA0 - Trigger 0 (Pattern A) */
- REGW(0x3d08a0, 0x8000000000000000);
+ REGW(0x3d08a0, 0x8000000000000000UL);
/* Init_70: CI Trc 0 - Mode */
- REGW(0x3d08b0, 0x8000000000000000);
+ REGW(0x3d08b0, 0x8000000000000000UL);
/* Init_71: CI Trc 0 CA1 - Pattern A (TX cmd val) */
- REGW(0x3d0900, 0xC0200000DFFFFF00);
+ REGW(0x3d0900, 0xC0200000DFFFFF00UL);
/* Init_72: CI Trc 0 CA1 - Trigger 0 (Pattern A) */
- REGW(0x3d0920, 0x8000000000000000);
+ REGW(0x3d0920, 0x8000000000000000UL);
/* Init_73: CI Trc 0 CA1 - Mode */
- REGW(0x3d0930, 0x8000000000000000);
+ REGW(0x3d0930, 0x8000000000000000UL);
/* Init_74: CI Trc 0 DBG - Run/Status (start trace) */
- REGW(0x3d0810, 0x8000000000000000);
+ REGW(0x3d0810, 0x8000000000000000UL);
/*** Setup Trace 1 ***/
/* Init_75: CI Trc 1 DBG - Run/Status (stop trace) */
- REGW(0x3d0c10, 0x5000000000000000);
+ REGW(0x3d0c10, 0x5000000000000000UL);
/* Init_76: CI Trc 1 DBG - Mode (not cross trig CA's) */
- REGW(0x3d0c08, 0xB0000000F0000000);
+ REGW(0x3d0c08, 0xB0000000F0000000UL);
/* Init_76a: CI Trc 1 DBG - C0 (stop on error) */
- REGW(0x3d0c18, 0xF4F00FFF00000000);
+ REGW(0x3d0c18, 0xF4F00FFF00000000UL);
/* Init_77: CI Trc 1 DBG - Select (port 1 mode 2) */
- REGW(0x3d0c78, 0x0102000000000000);
+ REGW(0x3d0c78, 0x0102000000000000UL);
/* Init_78: CI Trc 1 CA0 - Pattern A (RX cmd val) */
- REGW(0x3d0c80, 0xC0200000DFFFFF00);
+ REGW(0x3d0c80, 0xC0200000DFFFFF00UL);
/* Init_79: CI Trc 1 CA0 - Trigger 0 (Pattern A) */
- REGW(0x3d0ca0, 0x8000000000000000);
+ REGW(0x3d0ca0, 0x8000000000000000UL);
/* Init_80: CI Trc 1 CA0 - Mode */
- REGW(0x3d0cb0, 0x8000000000000000);
+ REGW(0x3d0cb0, 0x8000000000000000UL);
/* Init_81: CI Trc 1 CA1 - Pattern A (TX cmd val) */
- REGW(0x3d0d00, 0xC0200000DFFFFF00);
+ REGW(0x3d0d00, 0xC0200000DFFFFF00UL);
/* Init_82: CI Trc 1 CA1 - Trigger 0 (Pattern A) */
- REGW(0x3d0d20, 0x8000000000000000);
+ REGW(0x3d0d20, 0x8000000000000000UL);
/* Init_83: CI Trc 1 CA1 - Mode */
- REGW(0x3d0d30, 0x8000000000000000);
+ REGW(0x3d0d30, 0x8000000000000000UL);
/* Init_84: CI Trc 1 DBG - Run/Status (start trace) */
- REGW(0x3d0c10, 0x8000000000000000);
+ REGW(0x3d0c10, 0x8000000000000000UL);
/* Init_85...92:
*
@@ -756,82 +756,82 @@ static void p7ioc_init_CI(struct p7ioc *ioc)
/*** Set buffer allocations (credits) ***/
/* Init_93: CI Port 0 Rx Cmd Buffer Allocation */
- REGW(0x3d0050, 0x0808040400000000);
+ REGW(0x3d0050, 0x0808040400000000UL);
/* Init_94: CI Port 0 Rx Dat Buffer Allocation */
- REGW(0x3d0060, 0x0006000200000000);
+ REGW(0x3d0060, 0x0006000200000000UL);
/* Init_95: CI Port 1 Tx Cmd Buffer Allocation */
- REGW(0x3d1030, 0x0000040400000000);
+ REGW(0x3d1030, 0x0000040400000000UL);
/* Init_96: CI Port 1 Tx Dat Buffer Allocation */
- REGW(0x3d1040, 0x0000004800000000);
+ REGW(0x3d1040, 0x0000004800000000UL);
/* Init_97: CI Port 1 Rx Cmd Buffer Allocation */
- REGW(0x3d1050, 0x0008000000000000);
+ REGW(0x3d1050, 0x0008000000000000UL);
/* Init_98: CI Port 1 Rx Dat Buffer Allocation */
- REGW(0x3d1060, 0x0048000000000000);
+ REGW(0x3d1060, 0x0048000000000000UL);
/* Init_99: CI Port 2 Tx Cmd Buffer Allocation */
- REGW(0x3d2030, 0x0808080800000000);
+ REGW(0x3d2030, 0x0808080800000000UL);
/* Init_100: CI Port 2 Tx Dat Buffer Allocation */
- REGW(0x3d2040, 0x0086008200000000);
+ REGW(0x3d2040, 0x0086008200000000UL);
/* Init_101: CI Port 2 Rx Cmd Buffer Allocation */
- REGW(0x3d2050, 0x0808080800000000);
+ REGW(0x3d2050, 0x0808080800000000UL);
/* Init_102: CI Port 2 Rx Dat Buffer Allocation */
- REGW(0x3d2060, 0x8648000000000000);
+ REGW(0x3d2060, 0x8648000000000000UL);
/* Init_103: CI Port 3 Tx Cmd Buffer Allocation */
- REGW(0x3d3030, 0x0808080800000000);
+ REGW(0x3d3030, 0x0808080800000000UL);
/* Init_104: CI Port 3 Tx Dat Buffer Allocation */
- REGW(0x3d3040, 0x0086008200000000);
+ REGW(0x3d3040, 0x0086008200000000UL);
/* Init_105: CI Port 3 Rx Cmd Buffer Allocation */
- REGW(0x3d3050, 0x0808080800000000);
+ REGW(0x3d3050, 0x0808080800000000UL);
/* Init_106: CI Port 3 Rx Dat Buffer Allocation */
- REGW(0x3d3060, 0x8648000000000000);
+ REGW(0x3d3060, 0x8648000000000000UL);
/* Init_107: CI Port 4 Tx Cmd Buffer Allocation */
- REGW(0x3d4030, 0x0808080800000000);
+ REGW(0x3d4030, 0x0808080800000000UL);
/* Init_108: CI Port 4 Tx Dat Buffer Allocation */
- REGW(0x3d4040, 0x0086008200000000);
+ REGW(0x3d4040, 0x0086008200000000UL);
/* Init_109: CI Port 4 Rx Cmd Buffer Allocation */
- REGW(0x3d4050, 0x0808080800000000);
+ REGW(0x3d4050, 0x0808080800000000UL);
/* Init_110: CI Port 4 Rx Dat Buffer Allocation */
- REGW(0x3d4060, 0x8648000000000000);
+ REGW(0x3d4060, 0x8648000000000000UL);
/* Init_111: CI Port 5 Tx Cmd Buffer Allocation */
- REGW(0x3d5030, 0x0808080800000000);
+ REGW(0x3d5030, 0x0808080800000000UL);
/* Init_112: CI Port 5 Tx Dat Buffer Allocation */
- REGW(0x3d5040, 0x0086008200000000);
+ REGW(0x3d5040, 0x0086008200000000UL);
/* Init_113: CI Port 5 Rx Cmd Buffer Allocation */
- REGW(0x3d5050, 0x0808080800000000);
+ REGW(0x3d5050, 0x0808080800000000UL);
/* Init_114: CI Port 5 Rx Dat Buffer Allocation */
- REGW(0x3d5060, 0x8648000000000000);
+ REGW(0x3d5060, 0x8648000000000000UL);
/* Init_115: CI Port 6 Tx Cmd Buffer Allocation */
- REGW(0x3d6030, 0x0808080800000000);
+ REGW(0x3d6030, 0x0808080800000000UL);
/* Init_116: CI Port 6 Tx Dat Buffer Allocation */
- REGW(0x3d6040, 0x0086008200000000);
+ REGW(0x3d6040, 0x0086008200000000UL);
/* Init_117: CI Port 6 Rx Cmd Buffer Allocation */
- REGW(0x3d6050, 0x0808080800000000);
+ REGW(0x3d6050, 0x0808080800000000UL);
/* Init_118: CI Port 6 Rx Dat Buffer Allocation */
- REGW(0x3d6060, 0x8648000000000000);
+ REGW(0x3d6060, 0x8648000000000000UL);
/* Init_119: CI Port 7 Tx Cmd Buffer Allocation */
- REGW(0x3d7030, 0x0808080800000000);
+ REGW(0x3d7030, 0x0808080800000000UL);
/* Init_120: CI Port 7 Tx Dat Buffer Allocation */
- REGW(0x3d7040, 0x0086008200000000);
+ REGW(0x3d7040, 0x0086008200000000UL);
/* Init_121: CI Port 7 Rx Cmd Buffer Allocation */
- REGW(0x3d7050, 0x0808080800000000);
+ REGW(0x3d7050, 0x0808080800000000UL);
/* Init_122: CI Port 6 Rx Dat Buffer Allocation */
- REGW(0x3d7060, 0x8648000000000000);
+ REGW(0x3d7060, 0x8648000000000000UL);
/*** Channel ordering ***/
/* Init_123: CI Port 1 Ordering */
- REGW(0x3d1070, 0x73D0735E00000000);
+ REGW(0x3d1070, 0x73D0735E00000000UL);
/* Init_124: CI Port 2 Ordering */
- REGW(0x3d2070, 0x73D0735E00000000);
+ REGW(0x3d2070, 0x73D0735E00000000UL);
/* Init_125: CI Port 3 Ordering */
- REGW(0x3d3070, 0x73D0735E00000000);
+ REGW(0x3d3070, 0x73D0735E00000000UL);
/* Init_126: CI Port 4 Ordering */
- REGW(0x3d4070, 0x73D0735E00000000);
+ REGW(0x3d4070, 0x73D0735E00000000UL);
/* Init_127: CI Port 5 Ordering */
- REGW(0x3d5070, 0x73D0735E00000000);
+ REGW(0x3d5070, 0x73D0735E00000000UL);
/* Init_128: CI Port 6 Ordering */
- REGW(0x3d6070, 0x73D0735E00000000);
+ REGW(0x3d6070, 0x73D0735E00000000UL);
/* Init_129: CI POrt 7 Ordering */
- REGW(0x3d7070, 0x73D0735E00000000);
+ REGW(0x3d7070, 0x73D0735E00000000UL);
/*** Setup routing (port 0 only) */
@@ -843,21 +843,21 @@ static void p7ioc_init_CI(struct p7ioc *ioc)
*/
/* Init_226: CI Port 1 Configuration */
- REGW(0x3d1000, 0x023F0FCF07200002);
+ REGW(0x3d1000, 0x023F0FCF07200002UL);
/* Init_227: CI Port 2 Configuration */
- REGW(0x3d2000, 0x023F00C307200002);
+ REGW(0x3d2000, 0x023F00C307200002UL);
/* Init_228: CI Port 3 Configuration */
- REGW(0x3d3000, 0x023F00C307200002);
+ REGW(0x3d3000, 0x023F00C307200002UL);
/* Init_229: CI Port 4 Configuration */
- REGW(0x3d4000, 0x023F00C307200002);
+ REGW(0x3d4000, 0x023F00C307200002UL);
/* Init_230: CI Port 5 Configuration */
- REGW(0x3d5000, 0x023F00C307200002);
+ REGW(0x3d5000, 0x023F00C307200002UL);
/* Init_231: CI Port 6 Configuration */
- REGW(0x3d6000, 0x023F00C307200002);
+ REGW(0x3d6000, 0x023F00C307200002UL);
/* Init_232: CI Port 7 Configuration */
- REGW(0x3d7000, 0x023F00C307200002);
+ REGW(0x3d7000, 0x023F00C307200002UL);
/* Init_233: CI Port 0 Configuration */
- REGW(0x3d0000, 0x023F00C0073F0002);
+ REGW(0x3d0000, 0x023F00C0073F0002UL);
}
static void p7ioc_init_PHBs(struct p7ioc *ioc)
@@ -882,30 +882,30 @@ static void p7ioc_init_MISC(struct p7ioc *ioc)
/*** Set LEM regs ***/
/* Init_1: LEM FIR Accumulator */
- REGW(0x3ea000, 0x0000000000000000);
+ REGW(0x3ea000, 0x0000000000000000UL);
/* Init_2: LEM Action 0 */
- REGW(0x3ea030, 0xFFFFFFFCEE3FFFFF);
+ REGW(0x3ea030, 0xFFFFFFFCEE3FFFFFUL);
/* Init_3: LEM Action 1 */
- REGW(0x3ea038, 0x0000000001C00000);
+ REGW(0x3ea038, 0x0000000001C00000UL);
/* Init_4: LEM WOF */
- REGW(0x3ea040, 0x0000000000000000);
+ REGW(0x3ea040, 0x0000000000000000UL);
/* Init_5: LEM Mask (AND write) */
- REGW(0x3ea020, 0x000F03F0CD3FFFFF);
+ REGW(0x3ea020, 0x000F03F0CD3FFFFFUL);
/* Init_5.1: I2C LEM FIR Accumulator */
- REGW(0x3eb000, 0x0000000000000000);
+ REGW(0x3eb000, 0x0000000000000000UL);
/* Init_5.2: I2C LEM Action 0 */
- REGW(0x3eb030, 0xEE00000000000000);
+ REGW(0x3eb030, 0xEE00000000000000UL);
/* Init_5.3: I2C LEM Action 1 */
- REGW(0x3eb038, 0x0000000000000000);
+ REGW(0x3eb038, 0x0000000000000000UL);
/* Init_5.4: I2C LEM WOF */
- REGW(0x3eb040, 0x0000000000000000);
+ REGW(0x3eb040, 0x0000000000000000UL);
/* Init_5.5: I2C LEM Mask (AND write) */
- REGW(0x3eb020, 0x4600000000000000);
+ REGW(0x3eb020, 0x4600000000000000UL);
/*** Set RGC GP bits (error enables) ***/
/* Init_7: RGC GP0 control (enable umux errors) */
- REGW(0x3e1018, 0x8888880000000000);
+ REGW(0x3e1018, 0x8888880000000000ULL);
/*** Central Trace Setup ***
*
@@ -914,120 +914,120 @@ static void p7ioc_init_MISC(struct p7ioc *ioc)
*/
/* Init_8: */
- REGW(0x3ea810, 0x5000000000000000);
+ REGW(0x3ea810, 0x5000000000000000UL);
/* Init_9: */
- REGW(0x3ea800, 0x0000000000000000);
+ REGW(0x3ea800, 0x0000000000000000UL);
/* Init_10: */
- REGW(0x3ea808, 0xB0000000F0000000);
+ REGW(0x3ea808, 0xB0000000F0000000UL);
/* Init_11: */
- REGW(0x3ea818, 0xF4F00FFF00000000);
+ REGW(0x3ea818, 0xF4F00FFF00000000UL);
/* Init_12: */
- REGW(0x3ea820, 0x0000000000000000);
+ REGW(0x3ea820, 0x0000000000000000UL);
/* Init_13: */
- REGW(0x3ea828, 0x0000000000000000);
+ REGW(0x3ea828, 0x0000000000000000UL);
/* Init_14: */
- REGW(0x3ea830, 0x0000000000000000);
+ REGW(0x3ea830, 0x0000000000000000UL);
/* Init_15: */
- REGW(0x3ea838, 0x0000000000000000);
+ REGW(0x3ea838, 0x0000000000000000UL);
/* Init_16: */
- REGW(0x3ea840, 0x0000000000000000);
+ REGW(0x3ea840, 0x0000000000000000UL);
/* Init_17: */
- REGW(0x3ea878, 0x0300000000000000);
+ REGW(0x3ea878, 0x0300000000000000UL);
/* Init_18: PHB0 mux select (Rx/Tx) */
- REGW(0x000F80, 0x0000000000000000);
+ REGW(0x000F80, 0x0000000000000000UL);
/* Init_19: PHB1 mux select (Rx/Tx) */
- REGW(0x010F80, 0x0000000000000000);
+ REGW(0x010F80, 0x0000000000000000UL);
/* Init_19.0: PHB2 mux select (Rx/Tx) */
- REGW(0x020F80, 0x0000000000000000);
+ REGW(0x020F80, 0x0000000000000000UL);
/* Init_19.1: PHB3 mux select (Rx/Tx) */
- REGW(0x030F80, 0x0000000000000000);
+ REGW(0x030F80, 0x0000000000000000UL);
/* Init_19.2: PHB4 mux select (Rx/Tx) */
- REGW(0x040F80, 0x0000000000000000);
+ REGW(0x040F80, 0x0000000000000000UL);
/* Init_19.3: PHB5 mux select (Rx/Tx) */
- REGW(0x050F80, 0x0000000000000000);
+ REGW(0x050F80, 0x0000000000000000UL);
/* Init_20: */
- REGW(0x3ea880, 0x40008000FF7F0000);
+ REGW(0x3ea880, 0x40008000FF7F0000UL);
/* Init_21: */
- REGW(0x3ea888, 0x0000000000000000);
+ REGW(0x3ea888, 0x0000000000000000UL);
/* Init_22: */
- REGW(0x3ea890, 0x0000000000000000);
+ REGW(0x3ea890, 0x0000000000000000UL);
/* Init_23: */
- REGW(0x3ea898, 0x0000000000000000);
+ REGW(0x3ea898, 0x0000000000000000UL);
/* Init_24: */
- REGW(0x3ea8a0, 0x8000000000000000);
+ REGW(0x3ea8a0, 0x8000000000000000UL);
/* Init_25: */
- REGW(0x3ea8a8, 0x0000000000000000);
+ REGW(0x3ea8a8, 0x0000000000000000UL);
/* Init_26: */
- REGW(0x3ea8b0, 0x8000000000000000);
+ REGW(0x3ea8b0, 0x8000000000000000UL);
/* Init_27: */
- REGW(0x3ea8b8, 0x0000000000000000);
+ REGW(0x3ea8b8, 0x0000000000000000UL);
/* Init_28: */
- REGW(0x3ea8c0, 0x0000000000000000);
+ REGW(0x3ea8c0, 0x0000000000000000UL);
/* Init_29: */
- REGW(0x3ea900, 0x40008000FF7F0000);
+ REGW(0x3ea900, 0x40008000FF7F0000UL);
/* Init_30: */
- REGW(0x3ea908, 0x0000000000000000);
+ REGW(0x3ea908, 0x0000000000000000UL);
/* Init_31: */
- REGW(0x3ea910, 0x0000000000000000);
+ REGW(0x3ea910, 0x0000000000000000UL);
/* Init_32: */
- REGW(0x3ea918, 0x0000000000000000);
+ REGW(0x3ea918, 0x0000000000000000UL);
/* Init_33: */
- REGW(0x3ea920, 0x8000000000000000);
+ REGW(0x3ea920, 0x8000000000000000UL);
/* Init_34: */
- REGW(0x3ea928, 0x0000000000000000);
+ REGW(0x3ea928, 0x0000000000000000UL);
/* Init_35: */
- REGW(0x3ea930, 0x8000000000000000);
+ REGW(0x3ea930, 0x8000000000000000UL);
/* Init_36: */
- REGW(0x3ea938, 0x0000000000000000);
+ REGW(0x3ea938, 0x0000000000000000UL);
/* Init_37: */
- REGW(0x3ea940, 0x0000000000000000);
+ REGW(0x3ea940, 0x0000000000000000UL);
/* Init_38: */
- REGW(0x3ea980, 0x40008000FF7F0000);
+ REGW(0x3ea980, 0x40008000FF7F0000UL);
/* Init_39: */
- REGW(0x3ea988, 0x0000000000000000);
+ REGW(0x3ea988, 0x0000000000000000UL);
/* Init_40: */
- REGW(0x3ea990, 0x0000000000000000);
+ REGW(0x3ea990, 0x0000000000000000UL);
/* Init_41: */
- REGW(0x3ea998, 0x0000000000000000);
+ REGW(0x3ea998, 0x0000000000000000UL);
/* Init_42: */
- REGW(0x3ea9a0, 0x8000000000000000);
+ REGW(0x3ea9a0, 0x8000000000000000UL);
/* Init_43: */
- REGW(0x3ea9a8, 0x0000000000000000);
+ REGW(0x3ea9a8, 0x0000000000000000UL);
/* Init_44: */
- REGW(0x3ea9b0, 0x8000000000000000);
+ REGW(0x3ea9b0, 0x8000000000000000UL);
/* Init_45: */
- REGW(0x3ea9b8, 0x0000000000000000);
+ REGW(0x3ea9b8, 0x0000000000000000UL);
/* Init_46: */
- REGW(0x3ea9c0, 0x0000000000000000);
+ REGW(0x3ea9c0, 0x0000000000000000UL);
/* Init_47: */
- REGW(0x3eaa00, 0x40008000FF7F0000);
+ REGW(0x3eaa00, 0x40008000FF7F0000UL);
/* Init_48: */
- REGW(0x3eaa08, 0x0000000000000000);
+ REGW(0x3eaa08, 0x0000000000000000UL);
/* Init_49: */
- REGW(0x3eaa10, 0x0000000000000000);
+ REGW(0x3eaa10, 0x0000000000000000UL);
/* Init_50: */
- REGW(0x3eaa18, 0x0000000000000000);
+ REGW(0x3eaa18, 0x0000000000000000UL);
/* Init_51: */
- REGW(0x3eaa20, 0x8000000000000000);
+ REGW(0x3eaa20, 0x8000000000000000UL);
/* Init_52: */
- REGW(0x3eaa28, 0x0000000000000000);
+ REGW(0x3eaa28, 0x0000000000000000UL);
/* Init_53: */
- REGW(0x3eaa30, 0x8000000000000000);
+ REGW(0x3eaa30, 0x8000000000000000UL);
/* Init_54: */
- REGW(0x3eaa38, 0x0000000000000000);
+ REGW(0x3eaa38, 0x0000000000000000UL);
/* Init_55: */
- REGW(0x3eaa40, 0x0000000000000000);
+ REGW(0x3eaa40, 0x0000000000000000UL);
/* Init_56: */
- REGW(0x3ea810, 0x1000000000000000);
+ REGW(0x3ea810, 0x1000000000000000UL);
/* Init_57: */
- REGW(0x3ea810, 0x8000000000000000);
+ REGW(0x3ea810, 0x8000000000000000UL);
/*** I2C Master init fixup */
/* Init_58: I2C Master Operation Control */
- REGW(0x3eb0a8, 0x8100000000000000);
+ REGW(0x3eb0a8, 0x8100000000000000UL);
}
static void p7ioc_init_GEM(struct p7ioc *ioc)
@@ -1055,7 +1055,7 @@ static void p7ioc_init_GEM(struct p7ioc *ioc)
/* Init_4: GEM XFIR */
REGW(0x3e0008, 0x0000000000000000);
/* Init_5: GEM Mask (See FIXME) */
- REGW(0x3e0020, 0x000F033FFFFFFFFF);
+ REGW(0x3e0020, 0x000F033FFFFFFFFFUL);
/* Init_6: GEM WOF */
REGW(0x3e0028, 0x0000000000000000);
}
diff --git a/hw/p7ioc-phb.c b/hw/p7ioc-phb.c
index 4ea0369cc476..66c166f7a74f 100644
--- a/hw/p7ioc-phb.c
+++ b/hw/p7ioc-phb.c
@@ -77,7 +77,7 @@ static bool p7ioc_phb_fenced(struct p7ioc_phb *p)
struct p7ioc *ioc = p->ioc;
uint64_t fence, fbits;
- fbits = 0x0003000000000000 >> (p->index * 4);
+ fbits = 0x0003000000000000UL >> (p->index * 4);
fence = in_be64(ioc->regs + P7IOC_CHIP_FENCE_SHADOW);
return (fence & fbits) != 0;
@@ -241,7 +241,7 @@ static int64_t p7ioc_sm_freset(struct p7ioc_phb *p)
}
/* Mask PCIE port interrupts and AER receiver error */
- out_be64(p->regs + UTL_PCIE_PORT_IRQ_EN, 0x7E00000000000000);
+ out_be64(p->regs + UTL_PCIE_PORT_IRQ_EN, 0x7E00000000000000UL);
p7ioc_pcicfg_read32(&p->phb, 0,
p->aercap + PCIECAP_AER_CE_MASK, &cfg32);
cfg32 |= PCIECAP_AER_CE_RECVR_ERR;
@@ -311,9 +311,9 @@ static int64_t p7ioc_sm_freset(struct p7ioc_phb *p)
* interrupts
*/
out_be64(p->regs + UTL_PCIE_PORT_STATUS,
- 0x00E0000000000000);
+ 0x00E0000000000000UL);
out_be64(p->regs + UTL_PCIE_PORT_IRQ_EN,
- 0xFE65000000000000);
+ 0xFE65000000000000UL);
/* Clear AER receiver error status */
p7ioc_pcicfg_write32(&p->phb, 0,
@@ -448,7 +448,7 @@ static int64_t p7ioc_sm_slot_power_off(struct p7ioc_phb *p)
* PHB slot. Otherwise, it won't take effect. That's the
* similar thing as we did for power-on.
*/
- out_be64(p->regs + UTL_PCIE_PORT_IRQ_EN, 0x7e00000000000000);
+ out_be64(p->regs + UTL_PCIE_PORT_IRQ_EN, 0x7e00000000000000UL);
reg = in_be64(p->regs + PHB_HOTPLUG_OVERRIDE);
reg &= ~(0x8c00000000000000ul);
reg |= 0x8400000000000000ul;
@@ -530,7 +530,7 @@ static int64_t p7ioc_sm_slot_power_on(struct p7ioc_phb *p)
/* Adjust UTL interrupt settings to disable various
* errors that would interfere with the process
*/
- out_be64(p->regs + UTL_PCIE_PORT_IRQ_EN, 0x7e00000000000000);
+ out_be64(p->regs + UTL_PCIE_PORT_IRQ_EN, 0x7e00000000000000UL);
/* If the power is not on, turn it on now */
if (!(reg & PHB_PCIE_SLOTCTL2_PWR_EN_STAT)) {
@@ -699,7 +699,7 @@ static int64_t p7ioc_sm_hot_reset(struct p7ioc_phb *p)
}
/* Mask PCIE port interrupts and AER receiver error */
- out_be64(p->regs + UTL_PCIE_PORT_IRQ_EN, 0x7E00000000000000);
+ out_be64(p->regs + UTL_PCIE_PORT_IRQ_EN, 0x7E00000000000000UL);
p7ioc_pcicfg_read32(&p->phb, 0,
p->aercap + PCIECAP_AER_CE_MASK, &cfg32);
cfg32 |= PCIECAP_AER_CE_RECVR_ERR;
@@ -760,8 +760,8 @@ static int64_t p7ioc_sm_hot_reset(struct p7ioc_phb *p)
* Clear spurious errors and enable PCIE port
* interrupts
*/
- out_be64(p->regs + UTL_PCIE_PORT_STATUS, 0x00E0000000000000);
- out_be64(p->regs + UTL_PCIE_PORT_IRQ_EN, 0xFE65000000000000);
+ out_be64(p->regs + UTL_PCIE_PORT_STATUS, 0x00E0000000000000UL);
+ out_be64(p->regs + UTL_PCIE_PORT_IRQ_EN, 0xFE65000000000000UL);
/* Clear AER receiver error status */
p7ioc_pcicfg_write32(&p->phb, 0,
@@ -1872,7 +1872,7 @@ static int64_t p7ioc_map_pe_dma_window(struct phb *phb, uint16_t pe_number,
case 0x1000000: /* 16M */
tvt1 = SETFIELD(IODA_TVT1_IO_PSIZE, 0ul, 13ul);
break;
- case 0x400000000: /* 16G */
+ case 0x400000000UL: /* 16G */
tvt1 = SETFIELD(IODA_TVT1_IO_PSIZE, 0ul, 23ul);
break;
default:
@@ -2344,7 +2344,7 @@ static void p7ioc_phb_init_ioda_cache(struct p7ioc_phb *p)
* last entry is to encompass all RIDs.
*/
for (i = 0; i < 127; i++)
- p->peltm_cache[i] = 0x0001f80000000000;
+ p->peltm_cache[i] = 0x0001f80000000000UL;
p->peltm_cache[127] = 0x0ul;
for (i = 0; i < 128; i++) {
@@ -3114,83 +3114,83 @@ static void p7ioc_phb_init_utl(struct p7ioc_phb *p)
/* Init_82..84: Clear spurious errors and assign errors to the
* right "interrupt" signal
*/
- out_be64(p->regs + UTL_SYS_BUS_AGENT_STATUS, 0xffffffffffffffff);
- out_be64(p->regs + UTL_SYS_BUS_AGENT_ERR_SEVERITY, 0x0000000000000000);
- out_be64(p->regs + UTL_SYS_BUS_AGENT_IRQ_EN, 0xac80000000000000);
+ out_be64(p->regs + UTL_SYS_BUS_AGENT_STATUS, 0xffffffffffffffffUL);
+ out_be64(p->regs + UTL_SYS_BUS_AGENT_ERR_SEVERITY, 0x0000000000000000UL);
+ out_be64(p->regs + UTL_SYS_BUS_AGENT_IRQ_EN, 0xac80000000000000UL);
/* Init_85..89: Setup buffer allocations */
- out_be64(p->regs + UTL_OUT_POST_DAT_BUF_ALLOC, 0x0400000000000000);
- out_be64(p->regs + UTL_IN_POST_HDR_BUF_ALLOC, 0x1000000000000000);
- out_be64(p->regs + UTL_IN_POST_DAT_BUF_ALLOC, 0x4000000000000000);
- out_be64(p->regs + UTL_PCIE_TAGS_ALLOC, 0x0800000000000000);
- out_be64(p->regs + UTL_GBIF_READ_TAGS_ALLOC, 0x0800000000000000);
+ out_be64(p->regs + UTL_OUT_POST_DAT_BUF_ALLOC, 0x0400000000000000UL);
+ out_be64(p->regs + UTL_IN_POST_HDR_BUF_ALLOC, 0x1000000000000000UL);
+ out_be64(p->regs + UTL_IN_POST_DAT_BUF_ALLOC, 0x4000000000000000UL);
+ out_be64(p->regs + UTL_PCIE_TAGS_ALLOC, 0x0800000000000000UL);
+ out_be64(p->regs + UTL_GBIF_READ_TAGS_ALLOC, 0x0800000000000000UL);
/* Init_90: PCI Express port control */
- out_be64(p->regs + UTL_PCIE_PORT_CONTROL, 0x8480000000000000);
+ out_be64(p->regs + UTL_PCIE_PORT_CONTROL, 0x8480000000000000UL);
/* Init_91..93: Clean & setup port errors */
- out_be64(p->regs + UTL_PCIE_PORT_STATUS, 0xff7fffffffffffff);
- out_be64(p->regs + UTL_PCIE_PORT_ERROR_SEV, 0x00e0000000000000);
- out_be64(p->regs + UTL_PCIE_PORT_IRQ_EN, 0x7e65000000000000);
+ out_be64(p->regs + UTL_PCIE_PORT_STATUS, 0xff7fffffffffffffUL);
+ out_be64(p->regs + UTL_PCIE_PORT_ERROR_SEV, 0x00e0000000000000UL);
+ out_be64(p->regs + UTL_PCIE_PORT_IRQ_EN, 0x7e65000000000000UL);
/* Init_94 : Cleanup RC errors */
- out_be64(p->regs + UTL_RC_STATUS, 0xffffffffffffffff);
+ out_be64(p->regs + UTL_RC_STATUS, 0xffffffffffffffffUL);
}
static void p7ioc_phb_init_errors(struct p7ioc_phb *p)
{
/* Init_98: LEM Error Mask : Temporarily disable error interrupts */
- out_be64(p->regs + PHB_LEM_ERROR_MASK, 0xffffffffffffffff);
+ out_be64(p->regs + PHB_LEM_ERROR_MASK, 0xffffffffffffffffUL);
/* Init_99..107: Configure main error traps & clear old state */
- out_be64(p->regs + PHB_ERR_STATUS, 0xffffffffffffffff);
- out_be64(p->regs + PHB_ERR1_STATUS, 0x0000000000000000);
- out_be64(p->regs + PHB_ERR_LEM_ENABLE, 0xffffffffefffffff);
- out_be64(p->regs + PHB_ERR_FREEZE_ENABLE, 0x0000000061c00000);
- out_be64(p->regs + PHB_ERR_AIB_FENCE_ENABLE, 0xffffffc58c000000);
- out_be64(p->regs + PHB_ERR_LOG_0, 0x0000000000000000);
- out_be64(p->regs + PHB_ERR_LOG_1, 0x0000000000000000);
- out_be64(p->regs + PHB_ERR_STATUS_MASK, 0x0000000000000000);
- out_be64(p->regs + PHB_ERR1_STATUS_MASK, 0x0000000000000000);
+ out_be64(p->regs + PHB_ERR_STATUS, 0xffffffffffffffffUL);
+ out_be64(p->regs + PHB_ERR1_STATUS, 0x0000000000000000UL);
+ out_be64(p->regs + PHB_ERR_LEM_ENABLE, 0xffffffffefffffffUL);
+ out_be64(p->regs + PHB_ERR_FREEZE_ENABLE, 0x0000000061c00000UL);
+ out_be64(p->regs + PHB_ERR_AIB_FENCE_ENABLE, 0xffffffc58c000000UL);
+ out_be64(p->regs + PHB_ERR_LOG_0, 0x0000000000000000UL);
+ out_be64(p->regs + PHB_ERR_LOG_1, 0x0000000000000000UL);
+ out_be64(p->regs + PHB_ERR_STATUS_MASK, 0x0000000000000000UL);
+ out_be64(p->regs + PHB_ERR1_STATUS_MASK, 0x0000000000000000UL);
/* Init_108_116: Configure MMIO error traps & clear old state */
- out_be64(p->regs + PHB_OUT_ERR_STATUS, 0xffffffffffffffff);
- out_be64(p->regs + PHB_OUT_ERR1_STATUS, 0x0000000000000000);
- out_be64(p->regs + PHB_OUT_ERR_LEM_ENABLE, 0xffffffffffffffff);
- out_be64(p->regs + PHB_OUT_ERR_FREEZE_ENABLE, 0x0000430803000000);
- out_be64(p->regs + PHB_OUT_ERR_AIB_FENCE_ENABLE, 0x9df3bc00f0f0700f);
- out_be64(p->regs + PHB_OUT_ERR_LOG_0, 0x0000000000000000);
- out_be64(p->regs + PHB_OUT_ERR_LOG_1, 0x0000000000000000);
- out_be64(p->regs + PHB_OUT_ERR_STATUS_MASK, 0x0000000000000000);
- out_be64(p->regs + PHB_OUT_ERR1_STATUS_MASK, 0x0000000000000000);
+ out_be64(p->regs + PHB_OUT_ERR_STATUS, 0xffffffffffffffffUL);
+ out_be64(p->regs + PHB_OUT_ERR1_STATUS, 0x0000000000000000UL);
+ out_be64(p->regs + PHB_OUT_ERR_LEM_ENABLE, 0xffffffffffffffffUL);
+ out_be64(p->regs + PHB_OUT_ERR_FREEZE_ENABLE, 0x0000430803000000UL);
+ out_be64(p->regs + PHB_OUT_ERR_AIB_FENCE_ENABLE, 0x9df3bc00f0f0700fUL);
+ out_be64(p->regs + PHB_OUT_ERR_LOG_0, 0x0000000000000000UL);
+ out_be64(p->regs + PHB_OUT_ERR_LOG_1, 0x0000000000000000UL);
+ out_be64(p->regs + PHB_OUT_ERR_STATUS_MASK, 0x0000000000000000UL);
+ out_be64(p->regs + PHB_OUT_ERR1_STATUS_MASK, 0x0000000000000000UL);
/* Init_117_125: Configure DMA_A error traps & clear old state */
- out_be64(p->regs + PHB_INA_ERR_STATUS, 0xffffffffffffffff);
- out_be64(p->regs + PHB_INA_ERR1_STATUS, 0x0000000000000000);
- out_be64(p->regs + PHB_INA_ERR_LEM_ENABLE, 0xffffffffffffffff);
- out_be64(p->regs + PHB_INA_ERR_FREEZE_ENABLE, 0xc00003ff01006000);
- out_be64(p->regs + PHB_INA_ERR_AIB_FENCE_ENABLE, 0x3fff50007e559fd8);
- out_be64(p->regs + PHB_INA_ERR_LOG_0, 0x0000000000000000);
- out_be64(p->regs + PHB_INA_ERR_LOG_1, 0x0000000000000000);
- out_be64(p->regs + PHB_INA_ERR_STATUS_MASK, 0x0000000000000000);
- out_be64(p->regs + PHB_INA_ERR1_STATUS_MASK, 0x0000000000000000);
+ out_be64(p->regs + PHB_INA_ERR_STATUS, 0xffffffffffffffffUL);
+ out_be64(p->regs + PHB_INA_ERR1_STATUS, 0x0000000000000000UL);
+ out_be64(p->regs + PHB_INA_ERR_LEM_ENABLE, 0xffffffffffffffffUL);
+ out_be64(p->regs + PHB_INA_ERR_FREEZE_ENABLE, 0xc00003ff01006000UL);
+ out_be64(p->regs + PHB_INA_ERR_AIB_FENCE_ENABLE, 0x3fff50007e559fd8UL);
+ out_be64(p->regs + PHB_INA_ERR_LOG_0, 0x0000000000000000UL);
+ out_be64(p->regs + PHB_INA_ERR_LOG_1, 0x0000000000000000UL);
+ out_be64(p->regs + PHB_INA_ERR_STATUS_MASK, 0x0000000000000000UL);
+ out_be64(p->regs + PHB_INA_ERR1_STATUS_MASK, 0x0000000000000000UL);
/* Init_126_134: Configure DMA_B error traps & clear old state */
- out_be64(p->regs + PHB_INB_ERR_STATUS, 0xffffffffffffffff);
- out_be64(p->regs + PHB_INB_ERR1_STATUS, 0x0000000000000000);
- out_be64(p->regs + PHB_INB_ERR_LEM_ENABLE, 0xffffffffffffffff);
- out_be64(p->regs + PHB_INB_ERR_FREEZE_ENABLE, 0x0000000000000000);
- out_be64(p->regs + PHB_INB_ERR_AIB_FENCE_ENABLE, 0x18ff80ffff7f0000);
- out_be64(p->regs + PHB_INB_ERR_LOG_0, 0x0000000000000000);
- out_be64(p->regs + PHB_INB_ERR_LOG_1, 0x0000000000000000);
- out_be64(p->regs + PHB_INB_ERR_STATUS_MASK, 0x0000000000000000);
- out_be64(p->regs + PHB_INB_ERR1_STATUS_MASK, 0x0000000000000000);
+ out_be64(p->regs + PHB_INB_ERR_STATUS, 0xffffffffffffffffUL);
+ out_be64(p->regs + PHB_INB_ERR1_STATUS, 0x0000000000000000UL);
+ out_be64(p->regs + PHB_INB_ERR_LEM_ENABLE, 0xffffffffffffffffUL);
+ out_be64(p->regs + PHB_INB_ERR_FREEZE_ENABLE, 0x0000000000000000UL);
+ out_be64(p->regs + PHB_INB_ERR_AIB_FENCE_ENABLE, 0x18ff80ffff7f0000UL);
+ out_be64(p->regs + PHB_INB_ERR_LOG_0, 0x0000000000000000UL);
+ out_be64(p->regs + PHB_INB_ERR_LOG_1, 0x0000000000000000UL);
+ out_be64(p->regs + PHB_INB_ERR_STATUS_MASK, 0x0000000000000000UL);
+ out_be64(p->regs + PHB_INB_ERR1_STATUS_MASK, 0x0000000000000000UL);
/* Init_135..138: Cleanup & configure LEM */
- out_be64(p->regs + PHB_LEM_FIR_ACCUM, 0x0000000000000000);
- out_be64(p->regs + PHB_LEM_ACTION0, 0xffffffffffffffff);
- out_be64(p->regs + PHB_LEM_ACTION1, 0x0000000000000000);
- out_be64(p->regs + PHB_LEM_WOF, 0x0000000000000000);
+ out_be64(p->regs + PHB_LEM_FIR_ACCUM, 0x0000000000000000UL);
+ out_be64(p->regs + PHB_LEM_ACTION0, 0xffffffffffffffffUL);
+ out_be64(p->regs + PHB_LEM_ACTION1, 0x0000000000000000UL);
+ out_be64(p->regs + PHB_LEM_WOF, 0x0000000000000000UL);
}
/* p7ioc_phb_init - Initialize the PHB hardware
@@ -3223,7 +3223,7 @@ int64_t p7ioc_phb_init(struct p7ioc_phb *p)
* Interrupt Request=1, TCE Read=3.
*/
/* Init_1: AIB TX Channel Mapping */
- out_be64(p->regs_asb + PHB_AIB_TX_CHAN_MAPPING, 0x0211300000000000);
+ out_be64(p->regs_asb + PHB_AIB_TX_CHAN_MAPPING, 0x0211300000000000UL);
/*
* This group of steps initializes the AIB RX credits for
@@ -3241,11 +3241,11 @@ int64_t p7ioc_phb_init(struct p7ioc_phb *p)
*/
/* Init_2: AIB RX Command Credit */
- out_be64(p->regs_asb + PHB_AIB_RX_CMD_CRED, 0x0020002000200001);
+ out_be64(p->regs_asb + PHB_AIB_RX_CMD_CRED, 0x0020002000200001UL);
/* Init_3: AIB RX Data Credit */
- out_be64(p->regs_asb + PHB_AIB_RX_DATA_CRED, 0x0000002000000001);
+ out_be64(p->regs_asb + PHB_AIB_RX_DATA_CRED, 0x0000002000000001UL);
/* Init_4: AXIB RX Credit Init Timer */
- out_be64(p->regs_asb + PHB_AIB_RX_CRED_INIT_TIMER, 0xFF00000000000000);
+ out_be64(p->regs_asb + PHB_AIB_RX_CRED_INIT_TIMER, 0xFF00000000000000UL);
/*
* Enable all 32 AIB and TCE tags.
@@ -3256,9 +3256,9 @@ int64_t p7ioc_phb_init(struct p7ioc_phb *p)
*/
/* Init_5: PHB - AIB Tag Enable Register */
- out_be64(p->regs_asb + PHB_AIB_TAG_ENABLE, 0xFFFFFFFF00000000);
+ out_be64(p->regs_asb + PHB_AIB_TAG_ENABLE, 0xFFFFFFFF00000000UL);
/* Init_6: PHB – TCE Tag Enable Register */
- out_be64(p->regs_asb + PHB_TCE_TAG_ENABLE, 0xFFFFFFFF00000000);
+ out_be64(p->regs_asb + PHB_TCE_TAG_ENABLE, 0xFFFFFFFF00000000UL);
/* Init_7: PCIE - System Configuration Register
*
@@ -3275,7 +3275,7 @@ int64_t p7ioc_phb_init(struct p7ioc_phb *p)
* reduced to the allowed ranges from 128B
* to 2KB if needed.
*/
- out_be64(p->regs + PHB_PCIE_SYSTEM_CONFIG, 0x422800FC20000000);
+ out_be64(p->regs + PHB_PCIE_SYSTEM_CONFIG, 0x422800FC20000000UL);
/* Init_8: PHB - PCI-E Reset Register
*
@@ -3291,7 +3291,7 @@ int64_t p7ioc_phb_init(struct p7ioc_phb *p)
* NOTE: We perform a PERST at the end of the init sequence so
* we could probably skip that link training.
*/
- out_be64(p->regs + PHB_RESET, 0xE800000000000000);
+ out_be64(p->regs + PHB_RESET, 0xE800000000000000UL);
/* Init_9: BUID
*
@@ -3331,19 +3331,19 @@ int64_t p7ioc_phb_init(struct p7ioc_phb *p)
p7ioc_ioda_reset(&p->phb, false);
/* Init_42..47: Clear UTL & DLP error log regs */
- out_be64(p->regs + PHB_PCIE_UTL_ERRLOG1, 0xffffffffffffffff);
- out_be64(p->regs + PHB_PCIE_UTL_ERRLOG2, 0xffffffffffffffff);
- out_be64(p->regs + PHB_PCIE_UTL_ERRLOG3, 0xffffffffffffffff);
- out_be64(p->regs + PHB_PCIE_UTL_ERRLOG4, 0xffffffffffffffff);
- out_be64(p->regs + PHB_PCIE_DLP_ERRLOG1, 0xffffffffffffffff);
- out_be64(p->regs + PHB_PCIE_DLP_ERRLOG2, 0xffffffffffffffff);
+ out_be64(p->regs + PHB_PCIE_UTL_ERRLOG1, 0xffffffffffffffffUL);
+ out_be64(p->regs + PHB_PCIE_UTL_ERRLOG2, 0xffffffffffffffffUL);
+ out_be64(p->regs + PHB_PCIE_UTL_ERRLOG3, 0xffffffffffffffffUL);
+ out_be64(p->regs + PHB_PCIE_UTL_ERRLOG4, 0xffffffffffffffffUL);
+ out_be64(p->regs + PHB_PCIE_DLP_ERRLOG1, 0xffffffffffffffffUL);
+ out_be64(p->regs + PHB_PCIE_DLP_ERRLOG2, 0xffffffffffffffffUL);
/* Init_48: Wait for DLP core to be out of reset */
if (!p7ioc_phb_wait_dlp_reset(p))
goto failed;
/* Init_49 - Clear port status */
- out_be64(p->regs + UTL_PCIE_PORT_STATUS, 0xffffffffffffffff);
+ out_be64(p->regs + UTL_PCIE_PORT_STATUS, 0xffffffffffffffffUL);
/* Init_50..81: Init root complex config space */
if (!p7ioc_phb_init_rc_cfg(p))
@@ -3353,7 +3353,7 @@ int64_t p7ioc_phb_init(struct p7ioc_phb *p)
p7ioc_phb_init_utl(p);
/* Init_95: PCI-E Reset, deassert reset for internal error macros */
- out_be64(p->regs + PHB_RESET, 0xe000000000000000);
+ out_be64(p->regs + PHB_RESET, 0xe000000000000000UL);
/* Init_96: PHB Control register. Various PHB settings:
*
@@ -3361,7 +3361,7 @@ int64_t p7ioc_phb_init(struct p7ioc_phb *p)
* - Enable all TCAM entries
* - Set failed DMA read requests to return Completer Abort on error
*/
- out_be64(p->regs + PHB_CONTROL, 0x7f38000000000000);
+ out_be64(p->regs + PHB_CONTROL, 0x7f38000000000000UL);
/* Init_97: Legacy Control register
*
@@ -3406,18 +3406,18 @@ int64_t p7ioc_phb_init(struct p7ioc_phb *p)
*/
/* Init_145..149: Enable error interrupts and LEM */
- out_be64(p->regs + PHB_ERR_IRQ_ENABLE, 0x0000000061c00000);
- out_be64(p->regs + PHB_OUT_ERR_IRQ_ENABLE, 0x0000430803000000);
- out_be64(p->regs + PHB_INA_ERR_IRQ_ENABLE, 0xc00003ff01006000);
- out_be64(p->regs + PHB_INB_ERR_IRQ_ENABLE, 0x0000000000000000);
- out_be64(p->regs + PHB_LEM_ERROR_MASK, 0x1249a1147f500f2c);
+ out_be64(p->regs + PHB_ERR_IRQ_ENABLE, 0x0000000061c00000UL);
+ out_be64(p->regs + PHB_OUT_ERR_IRQ_ENABLE, 0x0000430803000000UL);
+ out_be64(p->regs + PHB_INA_ERR_IRQ_ENABLE, 0xc00003ff01006000UL);
+ out_be64(p->regs + PHB_INB_ERR_IRQ_ENABLE, 0x0000000000000000UL);
+ out_be64(p->regs + PHB_LEM_ERROR_MASK, 0x1249a1147f500f2cUL);
/* Init_150: Enable DMA read/write TLP address speculation */
- out_be64(p->regs + PHB_TCE_PREFETCH, 0x0000c00000000000);
+ out_be64(p->regs + PHB_TCE_PREFETCH, 0x0000c00000000000UL);
/* Init_151..152: Set various timeouts */
- out_be64(p->regs + PHB_TIMEOUT_CTRL1, 0x1611112010200000);
- out_be64(p->regs + PHB_TIMEOUT_CTRL2, 0x0000561300000000);
+ out_be64(p->regs + PHB_TIMEOUT_CTRL1, 0x1611112010200000UL);
+ out_be64(p->regs + PHB_TIMEOUT_CTRL2, 0x0000561300000000UL);
/* Mark the PHB as functional which enables all the various sequences */
p->state = P7IOC_PHB_STATE_FUNCTIONAL;
diff --git a/hw/p7ioc.c b/hw/p7ioc.c
index c1a45141fa8a..959414221b2c 100644
--- a/hw/p7ioc.c
+++ b/hw/p7ioc.c
@@ -235,7 +235,7 @@ static int64_t p7ioc_rgc_set_xive(void *data, uint32_t isn,
}
/* Update the XIVE. Don't care HRT entry on P7IOC */
- out_be64(ioc->regs + 0x3e1820, (0x0002000000000000 | irq));
+ out_be64(ioc->regs + 0x3e1820, (0x0002000000000000UL | irq));
xive = in_be64(ioc->regs + 0x3e1830);
xive = SETFIELD(IODA_XIVT_SERVER, xive, m_server);
xive = SETFIELD(IODA_XIVT_PRIORITY, xive, m_prio);
@@ -276,26 +276,26 @@ static bool p7ioc_err_bit(struct p7ioc *ioc, uint64_t wof)
/* EI won't create interrupt yet */
break;
case P7IOC_ERR_SRC_RGC:
- severity[P7IOC_ERR_CLASS_GXE] = 0xF00086E0F4FCFFFF;
- severity[P7IOC_ERR_CLASS_RGA] = 0x0000010000000000;
- severity[P7IOC_ERR_CLASS_INF] = 0x0FFF781F0B030000;
+ severity[P7IOC_ERR_CLASS_GXE] = 0xF00086E0F4FCFFFFUL;
+ severity[P7IOC_ERR_CLASS_RGA] = 0x0000010000000000UL;
+ severity[P7IOC_ERR_CLASS_INF] = 0x0FFF781F0B030000UL;
break;
case P7IOC_ERR_SRC_BI_UP:
- severity[P7IOC_ERR_CLASS_GXE] = 0xF7FFFFFF7FFFFFFF;
- severity[P7IOC_ERR_CLASS_INF] = 0x0800000080000000;
+ severity[P7IOC_ERR_CLASS_GXE] = 0xF7FFFFFF7FFFFFFFUL;
+ severity[P7IOC_ERR_CLASS_INF] = 0x0800000080000000UL;
break;
case P7IOC_ERR_SRC_BI_DOWN:
- severity[P7IOC_ERR_CLASS_GXE] = 0xDFFFF7F35F8000BF;
- severity[P7IOC_ERR_CLASS_INF] = 0x2000080CA07FFF40;
+ severity[P7IOC_ERR_CLASS_GXE] = 0xDFFFF7F35F8000BFUL;
+ severity[P7IOC_ERR_CLASS_INF] = 0x2000080CA07FFF40UL;
break;
case P7IOC_ERR_SRC_CI_P0:
- severity[P7IOC_ERR_CLASS_GXE] = 0xF5FF000000000000;
- severity[P7IOC_ERR_CLASS_INF] = 0x0200FFFFFFFFFFFF;
- severity[P7IOC_ERR_CLASS_MAL] = 0x0800000000000000;
+ severity[P7IOC_ERR_CLASS_GXE] = 0xF5FF000000000000UL;
+ severity[P7IOC_ERR_CLASS_INF] = 0x0200FFFFFFFFFFFFUL;
+ severity[P7IOC_ERR_CLASS_MAL] = 0x0800000000000000UL;
break;
case P7IOC_ERR_SRC_CI_P1:
- severity[P7IOC_ERR_CLASS_GXE] = 0xFFFF000000000000;
- severity[P7IOC_ERR_CLASS_INF] = 0x0000FFFFFFFFFFFF;
+ severity[P7IOC_ERR_CLASS_GXE] = 0xFFFF000000000000UL;
+ severity[P7IOC_ERR_CLASS_INF] = 0x0000FFFFFFFFFFFFUL;
break;
case P7IOC_ERR_SRC_CI_P2:
case P7IOC_ERR_SRC_CI_P3:
@@ -303,19 +303,19 @@ static bool p7ioc_err_bit(struct p7ioc *ioc, uint64_t wof)
case P7IOC_ERR_SRC_CI_P5:
case P7IOC_ERR_SRC_CI_P6:
case P7IOC_ERR_SRC_CI_P7:
- severity[P7IOC_ERR_CLASS_GXE] = 0x5B0B000000000000;
- severity[P7IOC_ERR_CLASS_PHB] = 0xA4F4000000000000;
- severity[P7IOC_ERR_CLASS_INF] = 0x0000FFFFFFFFFFFF;
+ severity[P7IOC_ERR_CLASS_GXE] = 0x5B0B000000000000UL;
+ severity[P7IOC_ERR_CLASS_PHB] = 0xA4F4000000000000UL;
+ severity[P7IOC_ERR_CLASS_INF] = 0x0000FFFFFFFFFFFFUL;
break;
case P7IOC_ERR_SRC_MISC:
- severity[P7IOC_ERR_CLASS_GXE] = 0x0000000310000000;
- severity[P7IOC_ERR_CLASS_PLL] = 0x0000000001C00000;
- severity[P7IOC_ERR_CLASS_INF] = 0x555FFFF0EE3FFFFF;
- severity[P7IOC_ERR_CLASS_MAL] = 0xAAA0000C00000000;
+ severity[P7IOC_ERR_CLASS_GXE] = 0x0000000310000000UL;
+ severity[P7IOC_ERR_CLASS_PLL] = 0x0000000001C00000UL;
+ severity[P7IOC_ERR_CLASS_INF] = 0x555FFFF0EE3FFFFFUL;
+ severity[P7IOC_ERR_CLASS_MAL] = 0xAAA0000C00000000UL;
break;
case P7IOC_ERR_SRC_I2C:
- severity[P7IOC_ERR_CLASS_GXE] = 0x1100000000000000;
- severity[P7IOC_ERR_CLASS_INF] = 0xEEFFFFFFFFFFFFFF;
+ severity[P7IOC_ERR_CLASS_GXE] = 0x1100000000000000UL;
+ severity[P7IOC_ERR_CLASS_INF] = 0xEEFFFFFFFFFFFFFFUL;
break;
case P7IOC_ERR_SRC_PHB0:
case P7IOC_ERR_SRC_PHB1:
@@ -323,9 +323,9 @@ static bool p7ioc_err_bit(struct p7ioc *ioc, uint64_t wof)
case P7IOC_ERR_SRC_PHB3:
case P7IOC_ERR_SRC_PHB4:
case P7IOC_ERR_SRC_PHB5:
- severity[P7IOC_ERR_CLASS_PHB] = 0xADB650CB808DD051;
- severity[P7IOC_ERR_CLASS_ER] = 0x0000A0147F50092C;
- severity[P7IOC_ERR_CLASS_INF] = 0x52490F2000222682;
+ severity[P7IOC_ERR_CLASS_PHB] = 0xADB650CB808DD051UL;
+ severity[P7IOC_ERR_CLASS_ER] = 0x0000A0147F50092CUL;
+ severity[P7IOC_ERR_CLASS_INF] = 0x52490F2000222682UL;
break;
}
@@ -402,7 +402,7 @@ bool p7ioc_check_LEM(struct p7ioc *ioc,
/* IOC would be broken upon broken FIR */
fir = in_be64(base + P7IOC_LEM_FIR_OFFSET);
- if (fir == 0xffffffffffffffff) {
+ if (fir == 0xffffffffffffffffUL) {
ioc->err.err_src = P7IOC_ERR_SRC_NONE;
ioc->err.err_class = P7IOC_ERR_CLASS_GXE;
goto err;
@@ -509,7 +509,7 @@ static bool p7ioc_check_GEM(struct p7ioc *ioc)
* Recov_6: go to GXE recovery?
*/
xfir = in_be64(ioc->regs + P7IOC_GEM_XFIR);
- if (xfir == 0xffffffffffffffff) {
+ if (xfir == 0xffffffffffffffffUL) {
ioc->err.err_src = P7IOC_ERR_SRC_NONE;
ioc->err.err_class = P7IOC_ERR_CLASS_GXE;
p7ioc_set_err_pending(ioc, true);
--
2.1.4
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