[Skiboot] [PATCH] add NX register defines
Dan Streetman
ddstreet at ieee.org
Fri Mar 27 15:43:55 AEDT 2015
This only adds defines for various NX registers and their bit values. This
doesn't add any code that uses them, and it's possible skiboot won't need to
use any of these registers, as they're the error and status registers, which
will be monitored/handled from the FSP. So this patch isn't required to add;
I added all these while I still thought the kernel driver needed to handle
them, and I hate to just throw their definitions away ;-) If skiboot ever
does need to use any of the status or err registers, the definitions will
already be in place with this patch.
This patch shouldn't actually affect the compiled binary at all, since it's
only adding unused defines.
Signed-off-by: Dan Streetman <ddstreet at ieee.org>
---
include/nx.h | 120 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 120 insertions(+)
diff --git a/include/nx.h b/include/nx.h
index 08a6165..0599a62 100644
--- a/include/nx.h
+++ b/include/nx.h
@@ -102,6 +102,126 @@
#define NX_CRB_IQ_SYM PPC_BITMASK(0, 2)
#define NX_CRB_IQ_ASYM PPC_BITMASK(3, 5)
+/* NX Status Register */
+#define NX_P7_STATUS NX_P7_SAT(0x1, 0x00)
+#define NX_P8_STATUS NX_P8_SAT(0x1, 0x00)
+#define NX_STATUS_HMI_ACTIVE PPC_BIT(54)
+#define NX_STATUS_PBI_IDLE PPC_BIT(55)
+#define NX_STATUS_DMA_CH0_IDLE PPC_BIT(56)
+#define NX_STATUS_DMA_CH1_IDLE PPC_BIT(57)
+#define NX_STATUS_DMA_CH2_IDLE PPC_BIT(58)
+#define NX_STATUS_DMA_CH3_IDLE PPC_BIT(59)
+#define NX_STATUS_DMA_CH4_IDLE PPC_BIT(60)
+#define NX_STATUS_DMA_CH5_IDLE PPC_BIT(61)
+#define NX_STATUS_DMA_CH6_IDLE PPC_BIT(62)
+#define NX_STATUS_DMA_CH7_IDLE PPC_BIT(63)
+
+/* Channel Status Registers */
+#define NX_P7_CH_CRB(ch) NX_P7_SAT(0x1, 0x03 + ((ch) * 2))
+#define NX_P8_CH_CRB(ch) NX_P8_SAT(0x1, 0x03 + ((ch) * 2))
+#define NX_P7_CH_STATUS(ch) NX_P7_SAT(0x1, 0x04 + ((ch) * 2))
+#define NX_P8_CH_STATUS(ch) NX_P8_SAT(0x1, 0x04 + ((ch) * 2))
+#define NX_CH_STATUS_ABORT PPC_BIT(0)
+#define NX_CH_STATUS_CCB_VALID PPC_BIT(4)
+#define NX_CH_STATUS_CCB_CM PPC_BITMASK(5, 7)
+#define NX_CH_STATUS_CCB_PRIO PPC_BITMASK(8, 15)
+#define NX_CH_STATUS_CCB_SN PPC_BITMASK(16, 31)
+#define NX_CH_STATUS_VALID PPC_BIT(32)
+#define NX_CH_STATUS_LPID PPC_BITMASK(38, 47)
+#define NX_CH_STATUS_CCB_ISN PPC_BITMASK(50, 63)
+#define NX_CH_STATUS_CRB_SJT PPC_BITMASK(50, 63)
+
+/* Kill Register */
+#define NX_P7_CRB_KILL NX_P7_SAT(0x1, 0x13)
+#define NX_P8_CRB_KILL NX_P8_SAT(0x1, 0x13)
+#define NX_CRB_KILL_LPID_KILL PPC_BIT(0)
+#define NX_CRB_KILL_LPID PPC_BITMASK(6, 15)
+#define NX_CRB_KILL_ISN_KILL PPC_BIT(16)
+#define NX_CRB_KILL_SJT_KILL PPC_BIT(17)
+#define NX_CRB_KILL_ISN PPC_BITMASK(18, 31)
+#define NX_CRB_KILL_SJT PPC_BITMASK(18, 31)
+#define NX_CRB_KILL_DONE PPC_BIT(32)
+#define NX_CRB_KILL_PBI_LOC PPC_BITMASK(40, 47)
+#define NX_CRB_KILL_PREFETCH_CH PPC_BITMASK(48, 55)
+#define NX_CRB_KILL_ALG_CH PPC_BITMASK(56, 63)
+
+/* Fault Isolation Registers (FIR) */
+#define NX_P7_DE_FIR_DATA NX_P7_SAT(0x4, 0x00)
+#define NX_P8_DE_FIR_DATA NX_P8_SAT(0x4, 0x00)
+#define NX_P7_DE_FIR_DATA_CLR NX_P7_SAT(0x4, 0x01)
+#define NX_P8_DE_FIR_DATA_CLR NX_P8_SAT(0x4, 0x01)
+#define NX_P7_DE_FIR_DATA_SET NX_P7_SAT(0x4, 0x02)
+#define NX_P8_DE_FIR_DATA_SET NX_P8_SAT(0x4, 0x02)
+#define NX_P7_DE_FIR_MASK NX_P7_SAT(0x4, 0x06)
+#define NX_P8_DE_FIR_MASK NX_P8_SAT(0x4, 0x03)
+#define NX_P7_DE_FIR_MASK_CLR NX_P7_SAT(0x4, 0x07)
+#define NX_P8_DE_FIR_MASK_CLR NX_P8_SAT(0x4, 0x04)
+#define NX_P7_DE_FIR_MASK_SET NX_P7_SAT(0x4, 0x08)
+#define NX_P8_DE_FIR_MASK_SET NX_P8_SAT(0x4, 0x05)
+#define NX_P7_DE_FIR_ACTION0 NX_P7_SAT(0x4, 0x03)
+#define NX_P8_DE_FIR_ACTION0 NX_P8_SAT(0x4, 0x06)
+#define NX_P7_DE_FIR_ACTION1 NX_P7_SAT(0x4, 0x04)
+#define NX_P8_DE_FIR_ACTION1 NX_P8_SAT(0x4, 0x07)
+#define NX_P7_DE_FIR_WOF NX_P7_SAT(0x4, 0x05)
+#define NX_P8_DE_FIR_WOF NX_P8_SAT(0x4, 0x08)
+#define NX_P7_PB_FIR_DATA NX_P7_SAT(0x2, 0x00)
+#define NX_P8_PB_FIR_DATA NX_P8_SAT(0x2, 0x00)
+#define NX_P7_PB_FIR_DATA_CLR NX_P7_SAT(0x2, 0x01)
+#define NX_P8_PB_FIR_DATA_CLR NX_P8_SAT(0x2, 0x01)
+#define NX_P7_PB_FIR_DATA_SET NX_P7_SAT(0x2, 0x02)
+#define NX_P8_PB_FIR_DATA_SET NX_P8_SAT(0x2, 0x02)
+#define NX_P7_PB_FIR_MASK NX_P7_SAT(0x2, 0x06)
+#define NX_P8_PB_FIR_MASK NX_P8_SAT(0x2, 0x03)
+#define NX_P7_PB_FIR_MASK_CLR NX_P7_SAT(0x2, 0x07)
+#define NX_P8_PB_FIR_MASK_CLR NX_P8_SAT(0x2, 0x04)
+#define NX_P7_PB_FIR_MASK_SET NX_P7_SAT(0x2, 0x08)
+#define NX_P8_PB_FIR_MASK_SET NX_P8_SAT(0x2, 0x05)
+#define NX_P7_PB_FIR_ACTION0 NX_P7_SAT(0x2, 0x03)
+#define NX_P8_PB_FIR_ACTION0 NX_P8_SAT(0x2, 0x06)
+#define NX_P7_PB_FIR_ACTION1 NX_P7_SAT(0x2, 0x04)
+#define NX_P8_PB_FIR_ACTION1 NX_P8_SAT(0x2, 0x07)
+#define NX_P7_PB_FIR_WOF NX_P7_SAT(0x2, 0x05)
+#define NX_P8_PB_FIR_WOF NX_P8_SAT(0x2, 0x08)
+#define NX_FIR_MCD_PB_CMD_HANG PPC_BIT(0) /* P7 only */
+#define NX_FIR_SHM_INV PPC_BIT(1)
+#define NX_FIR_MCD_ARRAY_ECC_CE PPC_BIT(2) /* P7 only */
+#define NX_FIR_MCD_ARRAY_ECC_UE PPC_BIT(3) /* P7 only */
+#define NX_FIR_CH0_ECC_CE PPC_BIT(4)
+#define NX_FIR_CH0_ECC_UE PPC_BIT(5)
+#define NX_FIR_CH1_ECC_CE PPC_BIT(6)
+#define NX_FIR_CH1_ECC_UE PPC_BIT(7)
+#define NX_FIR_DMA_NZ_CSB_CC PPC_BIT(8) /* lab use only */
+#define NX_FIR_DMA_ARRAY_ECC_CE PPC_BIT(9)
+#define NX_FIR_DMA_RW_ECC_CE PPC_BIT(10)
+#define NX_FIR_CH5_ECC_CE PPC_BIT(11)
+#define NX_FIR_CH6_ECC_CE PPC_BIT(12)
+#define NX_FIR_CH7_ECC_CE PPC_BIT(13)
+#define NX_FIR_OTHER_SCOM_ERR PPC_BIT(14)
+#define NX_FIR_DMA_INV_STATE PPC_BITMASK(15, 16)
+#define NX_FIR_DMA_ARRAY_ECC_UE PPC_BIT(17)
+#define NX_FIR_DMA_RW_ECC_UE PPC_BIT(18)
+#define NX_FIR_HYP PPC_BIT(19) /* for HYP to force HMI */
+#define NX_FIR_CH0_INV_STATE PPC_BIT(20)
+#define NX_FIR_CH1_INV_STATE PPC_BIT(21)
+#define NX_FIR_CH2_INV_STATE PPC_BIT(22)
+#define NX_FIR_CH3_INV_STATE PPC_BIT(23)
+#define NX_FIR_CH4_INV_STATE PPC_BIT(24)
+#define NX_FIR_CH5_INV_STATE PPC_BIT(25)
+#define NX_FIR_CH6_INV_STATE PPC_BIT(26)
+#define NX_FIR_CH7_INV_STATE PPC_BIT(27)
+#define NX_FIR_CH5_ECC_UE PPC_BIT(28)
+#define NX_FIR_CH6_ECC_UE PPC_BIT(29)
+#define NX_FIR_CH7_ECC_UE PPC_BIT(30)
+#define NX_FIR_CRB_UE PPC_BIT(31)
+#define NX_FIR_CRB_SUE PPC_BIT(32)
+#define NX_FIR_DMA_RW_ECC_SUE PPC_BIT(33)
+#define NX_FIR_MCD_CFG_REG_PARITY PPC_BIT(34) /* P7 only */
+#define NX_FIR_MCD_RECOVERY_INV_STATE PPC_BIT(35) /* P7 only */
+#define NX_FIR_P7_PARITY PPC_BIT(36) /* P7 only */
+#define NX_FIR_CH4_ECC_CE PPC_BIT(36) /* P8 only */
+#define NX_FIR_CH5_ECC_UE_2 PPC_BIT(37) /* P8 only */
+#define NX_FIR_P8_PARITY PPC_BITMASK(48, 49)
+
/**************************************/
/* Register field values/restrictions */
--
2.1.0
More information about the Skiboot
mailing list