[Skiboot] [PATCH] add NX opal calls to get/set registers

Dan Streetman ddstreet at ieee.org
Wed Mar 25 05:26:53 AEDT 2015


On Tue, Mar 24, 2015 at 11:13 AM, Dan Streetman <ddstreet at ieee.org> wrote:
> On Tue, Mar 24, 2015 at 4:53 AM, Madhavan Srinivasan
> <maddy at linux.vnet.ibm.com> wrote:
>>
>>
>> On Tuesday 24 March 2015 01:44 PM, Dan Streetman wrote:
>>>
>>> This adds opal calls to get and set some of the main NX registers,
>>> specifically that are used to monitor the NX chip, check for NX
>>> errors, and recover from errors.
>>>
>>> It took a while to settle on the functions, especially the FIR functions,
>>> as there are quite a lot of FIR registers, and I didn't think it would be
>>> good to create a bunch of opal calls to r/w each individual register.
>>> So for the FIR registers, the opal calls take extra parameters to allow
>>> specifying the specific register.
>>>
>>> Note that in the kernel, I did split out the FIR register access into
>>> multiple functions, but each of those functions internally uses the
>>> common FIR r/w opal calls.
>>>
>>> Signed-off-by: Dan Streetman <ddstreet at ieee.org>
>>> ---
>>> I can change the opal calls, if there is a more sensible way to set
>>> them up to access the various NX registers...this seemed like the
>>> best way to do it, at least that I could come up with :-)
>>>
>>>   hw/nx.c        | 141 ++++++++++++++++++++++++++++++++++++++++++++++++++
>>>   include/nx.h   | 161
>>> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
>>>   include/opal.h |  26 +++++++++-
>>>   3 files changed, 327 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/hw/nx.c b/hw/nx.c
>>> index 83528d1..c402d1c 100644
>>> --- a/hw/nx.c
>>> +++ b/hw/nx.c
>>> @@ -21,12 +21,153 @@
>>>   #include <io.h>
>>>   #include <cpu.h>
>>>   #include <nx.h>
>>> +#include <opal.h>
>>> +#include <opal-api.h>
>>> +
>>> +static struct dt_node *nx_nodes[MAX_CHIPS];
>>> +
>>> +#define NX_NODE(id)            ((id) < MAX_CHIPS ? nx_nodes[id] : NULL)
>>> +#define NX_BASE_ADDR(node)     (dt_get_address((node), 0, NULL))
>>> +
>>> +#define NX_FIR_SRC(s, n)                                 \
>>> +       ((s) == OPAL_NX_FIR_SRC_DE ? NX_DE_FIR_##n :      \
>>> +        (s) == OPAL_NX_FIR_SRC_PB ? NX_PB_FIR_##n :      \
>>> +        OPAL_PARAMETER)
>>> +
>>> +static int nx_xscom_read(uint32_t chip_id, uint16_t reg, uint64_t *val)
>>> +{
>>> +       struct dt_node *node = NX_NODE(chip_id);
>>> +
>>
>> We can also do get_chip(chip_id)->devnode instead of array?
>
> ah of course, thanks i'll update it and resend.

so I looked at it more closely, and it's not the chip (xscom) devnode
we're using here, it's the ibm,power-nx devnode, which is under the
xscom devnode.  So if we use get_chip(), we would need to also do
dt_find_compatible_node() to find the ibm,power-nx subnode, for each
opal call.  So, for the extra 8*MAX_CHIPS = 512 bytes, we save
processing time on every nx opal call.  I think that's probably worth
it?  Unless we are really short on space in skiboot...?

>
>>
>>> +       if (!node)
>>> +               return OPAL_PARAMETER;
>>> +
>>> +       return xscom_read(chip_id, NX_BASE_ADDR(node) + reg, val);
>>> +}
>>> +
>>> +static int nx_xscom_write(uint32_t chip_id, uint16_t reg, uint64_t val)
>>> +{
>>> +       struct dt_node *node = NX_NODE(chip_id);
>>> +
>>> +       if (!node)
>>> +               return OPAL_PARAMETER;
>>> +
>>> +       return xscom_write(chip_id, NX_BASE_ADDR(node) + reg, val);
>>> +}
>>> +
>>> +#define __nx_get(chip_id, reg, val)                                    \
>>> +       (0 > (reg) ? (reg) : nx_xscom_read((chip_id), (reg), (val)))
>>> +#define __nx_set(chip_id, reg, val)                                    \
>>> +       (0 > (reg) ? (reg) : nx_xscom_write((chip_id), (reg), (val)))
>>> +
>>> +static int64_t opal_nx_get_status(uint32_t chip_id, uint64_t *status)
>>> +{
>>> +       return nx_xscom_read(chip_id, NX_STATUS, status);
>>> +}
>>> +opal_call(OPAL_NX_GET_STATUS, opal_nx_get_status, 2);
>>> +
>>> +static int64_t opal_nx_set_status(uint32_t chip_id, uint64_t status)
>>> +{
>>> +       return nx_xscom_write(chip_id, NX_STATUS, status);
>>> +}
>>> +opal_call(OPAL_NX_SET_STATUS, opal_nx_set_status, 2);
>>> +
>>> +static int64_t opal_nx_ch_crb_addr(uint32_t chip_id, uint16_t ch,
>>> +                                  uint64_t *addr)
>>> +{
>>> +       if (ch > 7)
>>> +               return OPAL_PARAMETER;
>>> +
>>> +       return nx_xscom_read(chip_id, NX_CH_CRB(ch), addr);
>>> +}
>>> +opal_call(OPAL_NX_CH_CRB_ADDR, opal_nx_ch_crb_addr, 3);
>>> +
>>> +static int64_t opal_nx_get_ch_status(uint32_t chip_id, uint16_t ch,
>>> +                                    uint64_t *status)
>>> +{
>>> +       if (ch > 7)
>>> +               return OPAL_PARAMETER;
>>> +
>>> +       return nx_xscom_read(chip_id, NX_CH_STATUS(ch), status);
>>> +}
>>> +opal_call(OPAL_NX_GET_CH_STATUS, opal_nx_get_ch_status, 3);
>>> +
>>> +static int64_t opal_nx_set_ch_status(uint32_t chip_id, uint16_t ch,
>>> +                                    uint64_t status)
>>> +{
>>> +       if (ch > 7)
>>> +               return OPAL_PARAMETER;
>>> +
>>> +       return nx_xscom_write(chip_id, NX_CH_STATUS(ch), status);
>>> +}
>>> +opal_call(OPAL_NX_SET_CH_STATUS, opal_nx_set_ch_status, 3);
>>> +
>>> +static int64_t opal_nx_get_crb_kill(uint32_t chip_id, uint64_t *kill)
>>> +{
>>> +       return nx_xscom_read(chip_id, NX_CRB_KILL, kill);
>>> +}
>>> +opal_call(OPAL_NX_GET_CRB_KILL, opal_nx_get_crb_kill, 2);
>>> +
>>> +static int64_t opal_nx_set_crb_kill(uint32_t chip_id, uint64_t kill)
>>> +{
>>> +       return nx_xscom_write(chip_id, NX_CRB_KILL, kill);
>>> +}
>>> +opal_call(OPAL_NX_SET_CRB_KILL, opal_nx_set_crb_kill, 2);
>>> +
>>> +static int64_t opal_nx_get_fir(uint32_t chip_id, uint16_t src, uint16_t
>>> reg,
>>> +                              uint64_t *fir)
>>> +{
>>> +       int r;
>>> +
>>> +       r = (reg == OPAL_NX_FIR_REG_DATA ? NX_FIR_SRC(src, DATA) :
>>> +            reg == OPAL_NX_FIR_REG_DMASK ? NX_FIR_SRC(src, MASK) :
>>> +            reg == OPAL_NX_FIR_REG_ACT0 ? NX_FIR_SRC(src, ACTION0) :
>>> +            reg == OPAL_NX_FIR_REG_ACT1 ? NX_FIR_SRC(src, ACTION1) :
>>> +            reg == OPAL_NX_FIR_REG_WOF ? NX_FIR_SRC(src, WOF) :
>>> +            OPAL_PARAMETER);
>>> +
>>> +       return __nx_get(chip_id, r, fir);
>>> +}
>>> +opal_call(OPAL_NX_GET_FIR, opal_nx_get_fir, 4);
>>> +
>>> +static int64_t opal_nx_set_fir(uint32_t chip_id, uint16_t src, uint16_t
>>> reg,
>>> +                              uint64_t fir)
>>> +{
>>> +       int r;
>>> +
>>> +       r = (reg == OPAL_NX_FIR_REG_DATA ? NX_FIR_SRC(src, DATA) :
>>> +            reg == OPAL_NX_FIR_REG_DMASK ? NX_FIR_SRC(src, MASK) :
>>> +            reg == OPAL_NX_FIR_REG_ACT0 ? NX_FIR_SRC(src, ACTION0) :
>>> +            reg == OPAL_NX_FIR_REG_ACT1 ? NX_FIR_SRC(src, ACTION1) :
>>> +            OPAL_PARAMETER);
>>> +
>>> +       return __nx_set(chip_id, r, fir);
>>> +}
>>> +opal_call(OPAL_NX_SET_FIR, opal_nx_set_fir, 4);
>>> +
>>> +static int64_t opal_nx_set_fir_bits(uint32_t chip_id, uint16_t src,
>>> +                                   uint16_t reg, uint8_t set, uint64_t
>>> fir)
>>> +{
>>> +       int r;
>>> +
>>> +       if (set > 1)
>>> +               return OPAL_PARAMETER;
>>> +
>>> +       r = (reg == OPAL_NX_FIR_REG_DATA && set ? NX_FIR_SRC(src,
>>> DATA_SET) :
>>> +            reg == OPAL_NX_FIR_REG_DATA && !set ? NX_FIR_SRC(src,
>>> DATA_CLR) :
>>> +            reg == OPAL_NX_FIR_REG_DMASK && set ? NX_FIR_SRC(src,
>>> MASK_SET) :
>>> +            reg == OPAL_NX_FIR_REG_DMASK && !set ? NX_FIR_SRC(src,
>>> MASK_CLR) :
>>> +            OPAL_PARAMETER);
>>> +
>>> +       return __nx_set(chip_id, r, fir);
>>> +}
>>> +opal_call(OPAL_NX_SET_FIR_BITS, opal_nx_set_fir_bits, 5);
>>>     void nx_init(void)
>>>   {
>>>         struct dt_node *node;
>>>         dt_for_each_compatible(dt_root, node, "ibm,power-nx") {
>>> +               nx_nodes[dt_get_chip_id(node)] = node;
>>>                 nx_create_rng_node(node);
>>>                 nx_create_crypto_node(node);
>>>                 nx_create_842_node(node);
>>> diff --git a/include/nx.h b/include/nx.h
>>> index cf887c0..a8c186e 100644
>>> --- a/include/nx.h
>>> +++ b/include/nx.h
>>> @@ -17,6 +17,8 @@
>>>   #ifndef __NX_H
>>>   #define __NX_H
>>>   +#include <chip.h>
>>> +
>>>   /*************************************/
>>>   /* Register addresses and bit fields */
>>>   /*************************************/
>>> @@ -24,9 +26,20 @@
>>>   #define NX_P7_SAT(sat, offset)        XSCOM_SAT(0x1, sat, offset)
>>>   #define NX_P8_SAT(sat, offset)        XSCOM_SAT(0xc, sat, offset)
>>>   +#define NX_PNUM(name)                                        \
>>> +       (proc_gen == proc_gen_p7 ? NX_P7_##name :       \
>>> +        proc_gen == proc_gen_p8 ? NX_P8_##name :       \
>>> +        NX_P8_##name) /* default to P8 */
>>> +#define NX_PNUM_ARGS(name, ...)                                        \
>>> +       (proc_gen == proc_gen_p7 ? NX_P7_##name(__VA_ARGS__) :  \
>>> +        proc_gen == proc_gen_p8 ? NX_P8_##name(__VA_ARGS__) :  \
>>> +        NX_P8_##name(__VA_ARGS__)) /* default to P8 */
>>> +
>>> +
>>>   /* Random Number Generator */
>>>   #define NX_P7_RNG_BAR         NX_P7_SAT(0x2, 0x0c)
>>>   #define NX_P8_RNG_BAR         NX_P8_SAT(0x2, 0x0d)
>>> +#define NX_RNG_BAR             NX_PNUM(RNG_BAR)
>>>   #define   NX_P7_RNG_BAR_ADDR          PPC_BITMASK(18, 51)
>>>   #define   NX_P8_RNG_BAR_ADDR          PPC_BITMASK(14, 51)
>>>   #define   NX_RNG_BAR_SIZE             PPC_BITMASK(53, 55)
>>> @@ -34,11 +47,13 @@
>>>     #define NX_P7_RNG_CFG               NX_P7_SAT(0x2, 0x12)
>>>   #define NX_P8_RNG_CFG         NX_P8_SAT(0x2, 0x12)
>>> +#define NX_RNG_CFG             NX_PNUM(RNG_CFG)
>>>   #define   NX_RNG_CFG_ENABLE           PPC_BIT(63)
>>>     /* Symmetric Crypto */
>>>   #define NX_P7_SYM_CFG         NX_P7_SAT(0x2, 0x09)
>>>   #define NX_P8_SYM_CFG         NX_P8_SAT(0x2, 0x0a)
>>> +#define NX_SYM_CFG             NX_PNUM(SYM_CFG)
>>>   #define   NX_SYM_CFG_CI                       PPC_BITMASK(2, 14)
>>>   #define   NX_SYM_CFG_CT                       PPC_BITMASK(18, 23)
>>>   #define   NX_SYM_CFG_FC_ENABLE                PPC_BITMASK(32, 39)
>>> @@ -47,6 +62,7 @@
>>>   /* Asymmetric Crypto */
>>>   #define NX_P7_ASYM_CFG                NX_P7_SAT(0x2, 0x0a)
>>>   #define NX_P8_ASYM_CFG                NX_P8_SAT(0x2, 0x0b)
>>> +#define NX_ASYM_CFG            NX_PNUM(ASYM_CFG)
>>>   #define   NX_ASYM_CFG_CI              PPC_BITMASK(2, 14)
>>>   #define   NX_ASYM_CFG_CT              PPC_BITMASK(18, 23)
>>>   #define   NX_ASYM_CFG_FC_ENABLE               PPC_BITMASK(32, 52)
>>> @@ -55,6 +71,7 @@
>>>   /* 842 Compression */
>>>   #define NX_P7_842_CFG         NX_P7_SAT(0x2, 0x0b)
>>>   #define NX_P8_842_CFG         NX_P8_SAT(0x2, 0x0c)
>>> +#define NX_842_CFG             NX_PNUM(842_CFG)
>>>   #define   NX_842_CFG_CI                       PPC_BITMASK(2, 14)
>>>   #define   NX_842_CFG_CT                       PPC_BITMASK(18, 23)
>>>   #define   NX_842_CFG_FC_ENABLE                PPC_BITMASK(32, 36)
>>> @@ -63,6 +80,7 @@
>>>   /* DMA */
>>>   #define NX_P7_DMA_CFG         NX_P7_SAT(0x1, 0x02)
>>>   #define NX_P8_DMA_CFG         NX_P8_SAT(0x1, 0x02)
>>> +#define NX_DMA_CFG             NX_PNUM(DMA_CFG)
>>>   #define   NX_P8_DMA_CFG_842_COMPRESS_PREFETCH PPC_BIT(23)
>>>   #define   NX_P8_DMA_CFG_842_DECOMPRESS_PREFETCH       PPC_BIT(24)
>>>   #define   NX_DMA_CFG_AES_SHA_MAX_RR           PPC_BITMASK(25, 28)
>>> @@ -86,6 +104,7 @@
>>>   /* Engine Enable Register */
>>>   #define NX_P7_EE_CFG          NX_P7_SAT(0x1, 0x01)
>>>   #define NX_P8_EE_CFG          NX_P8_SAT(0x1, 0x01)
>>> +#define NX_EE_CFG              NX_PNUM(EE_CFG)
>>>   #define   NX_EE_CFG_EFUSE             PPC_BIT(0)
>>>   #define   NX_EE_CFG_CH7                       PPC_BIT(53) /* AMF */
>>>   #define   NX_EE_CFG_CH6                       PPC_BIT(54) /* AMF */
>>> @@ -96,6 +115,148 @@
>>>   #define   NX_EE_CFG_CH1                       PPC_BIT(62) /* 842 */
>>>   #define   NX_EE_CFG_CH0                       PPC_BIT(63) /* 842 */
>>>   +/* NX Status Register */
>>> +#define NX_P7_STATUS           NX_P7_SAT(0x1, 0x00)
>>> +#define NX_P8_STATUS           NX_P8_SAT(0x1, 0x00)
>>> +#define NX_STATUS              NX_PNUM(STATUS)
>>> +#define   NX_STATUS_HMI_ACTIVE         PPC_BIT(54)
>>> +#define   NX_STATUS_PBI_IDLE           PPC_BIT(55)
>>> +#define   NX_STATUS_DMA_CH0_IDLE       PPC_BIT(56)
>>> +#define   NX_STATUS_DMA_CH1_IDLE       PPC_BIT(57)
>>> +#define   NX_STATUS_DMA_CH2_IDLE       PPC_BIT(58)
>>> +#define   NX_STATUS_DMA_CH3_IDLE       PPC_BIT(59)
>>> +#define   NX_STATUS_DMA_CH4_IDLE       PPC_BIT(60)
>>> +#define   NX_STATUS_DMA_CH5_IDLE       PPC_BIT(61)
>>> +#define   NX_STATUS_DMA_CH6_IDLE       PPC_BIT(62)
>>> +#define   NX_STATUS_DMA_CH7_IDLE       PPC_BIT(63)
>>> +
>>> +/* Channel Status Registers */
>>> +#define NX_P7_CH_CRB(ch)       NX_P7_SAT(0x1, 0x03 + ((ch) * 2))
>>> +#define NX_P8_CH_CRB(ch)       NX_P8_SAT(0x1, 0x03 + ((ch) * 2))
>>> +#define NX_CH_CRB(ch)          NX_PNUM_ARGS(CH_CRB, ch)
>>> +#define NX_P7_CH_STATUS(ch)    NX_P7_SAT(0x1, 0x04 + ((ch) * 2))
>>> +#define NX_P8_CH_STATUS(ch)    NX_P8_SAT(0x1, 0x04 + ((ch) * 2))
>>> +#define NX_CH_STATUS(ch)       NX_PNUM_ARGS(CH_STATUS, ch)
>>> +#define   NX_CH_STATUS_ABORT           PPC_BIT(0)
>>> +#define   NX_CH_STATUS_CCB_VALID       PPC_BIT(4)
>>> +#define   NX_CH_STATUS_CCB_CM          PPC_BITMASK(5, 7)
>>> +#define   NX_CH_STATUS_CCB_PRIO                PPC_BITMASK(8, 15)
>>> +#define   NX_CH_STATUS_CCB_SN          PPC_BITMASK(16, 31)
>>> +#define   NX_CH_STATUS_VALID           PPC_BIT(32)
>>> +#define   NX_CH_STATUS_LPID            PPC_BITMASK(38, 47)
>>> +#define   NX_CH_STATUS_CCB_ISN         PPC_BITMASK(50, 63)
>>> +#define   NX_CH_STATUS_CRB_SJT         PPC_BITMASK(50, 63)
>>> +
>>> +/* Kill Register */
>>> +#define NX_P7_CRB_KILL         NX_P7_SAT(0x1, 0x13)
>>> +#define NX_P8_CRB_KILL         NX_P8_SAT(0x1, 0x13)
>>> +#define NX_CRB_KILL            NX_PNUM(CRB_KILL)
>>> +#define   NX_CRB_KILL_LPID_KILL                PPC_BIT(0)
>>> +#define   NX_CRB_KILL_LPID             PPC_BITMASK(6, 15)
>>> +#define   NX_CRB_KILL_ISN_KILL         PPC_BIT(16)
>>> +#define   NX_CRB_KILL_SJT_KILL         PPC_BIT(17)
>>> +#define   NX_CRB_KILL_ISN              PPC_BITMASK(18, 31)
>>> +#define   NX_CRB_KILL_SJT              PPC_BITMASK(18, 31)
>>> +#define   NX_CRB_KILL_DONE             PPC_BIT(32)
>>> +#define   NX_CRB_KILL_PBI_LOC          PPC_BITMASK(40, 47)
>>> +#define   NX_CRB_KILL_PREFETCH_CH      PPC_BITMASK(48, 55)
>>> +#define   NX_CRB_KILL_ALG_CH           PPC_BITMASK(56, 63)
>>> +
>>> +/* Fault Isolation Registers (FIR) */
>>> +#define NX_P7_DE_FIR_DATA      NX_P7_SAT(0x4, 0x00)
>>> +#define NX_P8_DE_FIR_DATA      NX_P8_SAT(0x4, 0x00)
>>> +#define NX_DE_FIR_DATA         NX_PNUM(DE_FIR_DATA)
>>> +#define NX_P7_DE_FIR_DATA_CLR  NX_P7_SAT(0x4, 0x01)
>>> +#define NX_P8_DE_FIR_DATA_CLR  NX_P8_SAT(0x4, 0x01)
>>> +#define NX_DE_FIR_DATA_CLR     NX_PNUM(DE_FIR_DATA_CLR)
>>> +#define NX_P7_DE_FIR_DATA_SET  NX_P7_SAT(0x4, 0x02)
>>> +#define NX_P8_DE_FIR_DATA_SET  NX_P8_SAT(0x4, 0x02)
>>> +#define NX_DE_FIR_DATA_SET     NX_PNUM(DE_FIR_DATA_SET)
>>> +#define NX_P7_DE_FIR_MASK      NX_P7_SAT(0x4, 0x06)
>>> +#define NX_P8_DE_FIR_MASK      NX_P8_SAT(0x4, 0x03)
>>> +#define NX_DE_FIR_MASK         NX_PNUM(DE_FIR_MASK)
>>> +#define NX_P7_DE_FIR_MASK_CLR  NX_P7_SAT(0x4, 0x07)
>>> +#define NX_P8_DE_FIR_MASK_CLR  NX_P8_SAT(0x4, 0x04)
>>> +#define NX_DE_FIR_MASK_CLR     NX_PNUM(DE_FIR_MASK_CLR)
>>> +#define NX_P7_DE_FIR_MASK_SET  NX_P7_SAT(0x4, 0x08)
>>> +#define NX_P8_DE_FIR_MASK_SET  NX_P8_SAT(0x4, 0x05)
>>> +#define NX_DE_FIR_MASK_SET     NX_PNUM(DE_FIR_MASK_SET)
>>> +#define NX_P7_DE_FIR_ACTION0   NX_P7_SAT(0x4, 0x03)
>>> +#define NX_P8_DE_FIR_ACTION0   NX_P8_SAT(0x4, 0x06)
>>> +#define NX_DE_FIR_ACTION0      NX_PNUM(DE_FIR_ACTION0)
>>> +#define NX_P7_DE_FIR_ACTION1   NX_P7_SAT(0x4, 0x04)
>>> +#define NX_P8_DE_FIR_ACTION1   NX_P8_SAT(0x4, 0x07)
>>> +#define NX_DE_FIR_ACTION1      NX_PNUM(DE_FIR_ACTION1)
>>> +#define NX_P7_DE_FIR_WOF       NX_P7_SAT(0x4, 0x05)
>>> +#define NX_P8_DE_FIR_WOF       NX_P8_SAT(0x4, 0x08)
>>> +#define NX_DE_FIR_WOF          NX_PNUM(DE_FIR_WOF)
>>> +#define NX_P7_PB_FIR_DATA      NX_P7_SAT(0x2, 0x00)
>>> +#define NX_P8_PB_FIR_DATA      NX_P8_SAT(0x2, 0x00)
>>> +#define NX_PB_FIR_DATA         NX_PNUM(PB_FIR_DATA)
>>> +#define NX_P7_PB_FIR_DATA_CLR  NX_P7_SAT(0x2, 0x01)
>>> +#define NX_P8_PB_FIR_DATA_CLR  NX_P8_SAT(0x2, 0x01)
>>> +#define NX_PB_FIR_DATA_CLR     NX_PNUM(PB_FIR_DATA_CLR)
>>> +#define NX_P7_PB_FIR_DATA_SET  NX_P7_SAT(0x2, 0x02)
>>> +#define NX_P8_PB_FIR_DATA_SET  NX_P8_SAT(0x2, 0x02)
>>> +#define NX_PB_FIR_DATA_SET     NX_PNUM(PB_FIR_DATA_SET)
>>> +#define NX_P7_PB_FIR_MASK      NX_P7_SAT(0x2, 0x06)
>>> +#define NX_P8_PB_FIR_MASK      NX_P8_SAT(0x2, 0x03)
>>> +#define NX_PB_FIR_MASK         NX_PNUM(PB_FIR_MASK)
>>> +#define NX_P7_PB_FIR_MASK_CLR  NX_P7_SAT(0x2, 0x07)
>>> +#define NX_P8_PB_FIR_MASK_CLR  NX_P8_SAT(0x2, 0x04)
>>> +#define NX_PB_FIR_MASK_CLR     NX_PNUM(PB_FIR_MASK_CLR)
>>> +#define NX_P7_PB_FIR_MASK_SET  NX_P7_SAT(0x2, 0x08)
>>> +#define NX_P8_PB_FIR_MASK_SET  NX_P8_SAT(0x2, 0x05)
>>> +#define NX_PB_FIR_MASK_SET     NX_PNUM(PB_FIR_MASK_SET)
>>> +#define NX_P7_PB_FIR_ACTION0   NX_P7_SAT(0x2, 0x03)
>>> +#define NX_P8_PB_FIR_ACTION0   NX_P8_SAT(0x2, 0x06)
>>> +#define NX_PB_FIR_ACTION0      NX_PNUM(PB_FIR_ACTION0)
>>> +#define NX_P7_PB_FIR_ACTION1   NX_P7_SAT(0x2, 0x04)
>>> +#define NX_P8_PB_FIR_ACTION1   NX_P8_SAT(0x2, 0x07)
>>> +#define NX_PB_FIR_ACTION1      NX_PNUM(PB_FIR_ACTION1)
>>> +#define NX_P7_PB_FIR_WOF       NX_P7_SAT(0x2, 0x05)
>>> +#define NX_P8_PB_FIR_WOF       NX_P8_SAT(0x2, 0x08)
>>> +#define NX_PB_FIR_WOF          NX_PNUM(PB_FIR_WOF)
>>> +#define   NX_FIR_MCD_PB_CMD_HANG       PPC_BIT(0) /* P7 only */
>>> +#define   NX_FIR_SHM_INV               PPC_BIT(1)
>>> +#define   NX_FIR_MCD_ARRAY_ECC_CE      PPC_BIT(2) /* P7 only */
>>> +#define   NX_FIR_MCD_ARRAY_ECC_UE      PPC_BIT(3) /* P7 only */
>>> +#define   NX_FIR_CH0_ECC_CE            PPC_BIT(4)
>>> +#define   NX_FIR_CH0_ECC_UE            PPC_BIT(5)
>>> +#define   NX_FIR_CH1_ECC_CE            PPC_BIT(6)
>>> +#define   NX_FIR_CH1_ECC_UE            PPC_BIT(7)
>>> +#define   NX_FIR_DMA_NZ_CSB_CC         PPC_BIT(8) /* lab use only */
>>> +#define   NX_FIR_DMA_ARRAY_ECC_CE      PPC_BIT(9)
>>> +#define   NX_FIR_DMA_RW_ECC_CE         PPC_BIT(10)
>>> +#define   NX_FIR_CH5_ECC_CE            PPC_BIT(11)
>>> +#define   NX_FIR_CH6_ECC_CE            PPC_BIT(12)
>>> +#define   NX_FIR_CH7_ECC_CE            PPC_BIT(13)
>>> +#define   NX_FIR_OTHER_SCOM_ERR                PPC_BIT(14)
>>> +#define   NX_FIR_DMA_INV_STATE         PPC_BITMASK(15, 16)
>>> +#define   NX_FIR_DMA_ARRAY_ECC_UE      PPC_BIT(17)
>>> +#define   NX_FIR_DMA_RW_ECC_UE         PPC_BIT(18)
>>> +#define   NX_FIR_HYP                   PPC_BIT(19) /* for HYP to force
>>> HMI */
>>> +#define   NX_FIR_CH0_INV_STATE         PPC_BIT(20)
>>> +#define   NX_FIR_CH1_INV_STATE         PPC_BIT(21)
>>> +#define   NX_FIR_CH2_INV_STATE         PPC_BIT(22)
>>> +#define   NX_FIR_CH3_INV_STATE         PPC_BIT(23)
>>> +#define   NX_FIR_CH4_INV_STATE         PPC_BIT(24)
>>> +#define   NX_FIR_CH5_INV_STATE         PPC_BIT(25)
>>> +#define   NX_FIR_CH6_INV_STATE         PPC_BIT(26)
>>> +#define   NX_FIR_CH7_INV_STATE         PPC_BIT(27)
>>> +#define   NX_FIR_CH5_ECC_UE            PPC_BIT(28)
>>> +#define   NX_FIR_CH6_ECC_UE            PPC_BIT(29)
>>> +#define   NX_FIR_CH7_ECC_UE            PPC_BIT(30)
>>> +#define   NX_FIR_CRB_UE                        PPC_BIT(31)
>>> +#define   NX_FIR_CRB_SUE               PPC_BIT(32)
>>> +#define   NX_FIR_DMA_RW_ECC_SUE                PPC_BIT(33)
>>> +#define   NX_FIR_MCD_CFG_REG_PARITY    PPC_BIT(34) /* P7 only */
>>> +#define   NX_FIR_MCD_RECOVERY_INV_STATE        PPC_BIT(35) /* P7 only */
>>> +#define   NX_FIR_P7_PARITY             PPC_BIT(36) /* P7 only */
>>> +#define   NX_FIR_CH4_ECC_CE            PPC_BIT(36) /* P8 only */
>>> +#define   NX_FIR_CH5_ECC_UE_2          PPC_BIT(37) /* P8 only */
>>> +#define   NX_FIR_P8_PARITY             PPC_BITMASK(48, 49)
>>> +
>>>     /**************************************/
>>>   /* Register field values/restrictions */
>>> diff --git a/include/opal.h b/include/opal.h
>>> index 622e1d5..580f0fe 100644
>>> --- a/include/opal.h
>>> +++ b/include/opal.h
>>> @@ -167,7 +167,18 @@
>>>   #define OPAL_PRD_MSG                          113
>>>   #define OPAL_LEDS_GET_INDICATOR                       114
>>>   #define OPAL_LEDS_SET_INDICATOR                       115
>>> -#define OPAL_LAST                              115
>>> +#define OPAL_NX_GET_STATUS                     116
>>> +#define OPAL_NX_SET_STATUS                     117
>>> +#define OPAL_NX_CH_CRB_ADDR                    118
>>> +#define OPAL_NX_GET_CH_STATUS                  119
>>> +#define OPAL_NX_SET_CH_STATUS                  120
>>> +#define OPAL_NX_GET_CRB_KILL                   121
>>> +#define OPAL_NX_SET_CRB_KILL                   122
>>> +#define OPAL_NX_GET_FIR                                123
>>> +#define OPAL_NX_SET_FIR                                124
>>> +#define OPAL_NX_SET_FIR_BITS                   125
>>> +
>>> +#define OPAL_LAST                              125
>>>     /* Device tree flags */
>>>   @@ -947,6 +958,19 @@ struct opal_i2c_request {
>>>         __be64 buffer_ra;               /* Buffer real address */
>>>   };
>>>   +enum {
>>> +       OPAL_NX_FIR_SRC_DE      = 1, /* DMA and Engine */
>>> +       OPAL_NX_FIR_SRC_PB      = 2, /* PowerBus */
>>> +};
>>> +
>>> +enum {
>>> +       OPAL_NX_FIR_REG_DATA    = 1,
>>> +       OPAL_NX_FIR_REG_DMASK   = 2,
>>> +       OPAL_NX_FIR_REG_ACT0    = 3,
>>> +       OPAL_NX_FIR_REG_ACT1    = 4,
>>> +       OPAL_NX_FIR_REG_WOF     = 5,
>>> +};
>>> +
>>>   #endif /* __ASSEMBLY__ */
>>>     #endif /* __OPAL_H */
>>
>>


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