[Skiboot] [PATCH] Set proper value for RPR register

[Benjamin Herrenschmidt]

On Thu, 2015-06-18 at 08:11 -0400, Patrick Williams III wrote:
> Do you have code elsewhere to set the register in the SLW?  You need
> to update the SLW as well. Though, I think the RPR is only cleared on
> winkle and not sleep. 

It's not in the list for the SLW, at least not with my current copy of
p8_pore_table_static_data.c, but it's been a while since I've resynced
this with the HWP's...

However, I believe Linux restores it on the way back from winkle.

Cheers,
Ben.

> Patrick Williams
> Sent from my iPhone
> 
> On Jun 18, 2015, at 12:30 AM, Benjamin Herrenschmidt
> <benh at kernel.crashing.org> wrote:
> 
> 
> > The value was provided by Dave Larson and is what pHyp uses
> > 
> > Signed-off-by: Benjamin Herrenschmidt <benh at kernel.crashing.org>
> > ---
> > diff --git a/asm/head.S b/asm/head.S
> > index fd6e3fb..6963188 100644
> > --- a/asm/head.S
> > +++ b/asm/head.S
> > @@ -707,6 +707,9 @@ init_shared_sprs:
> >    sync
> >    mtspr    SPR_HMEER,%r3
> >    isync
> > +    /* RPR (per-LPAR but let's treat it as replicated for now) */
> > +    LOAD_IMM64(%r3,0x00000103070F1F3F)
> > +    mtspr    SPR_RPR,%r3
> > 9:    blr
> > 
> > .global init_replicated_sprs
> > diff --git a/include/processor.h b/include/processor.h
> > index c9e9d0e..e8f0c3c 100644
> > --- a/include/processor.h
> > +++ b/include/processor.h
> > @@ -52,6 +52,7 @@
> > #define SPR_SRR0    0x01a    /* RW: Exception save/restore reg 0 */
> > #define SPR_SRR1    0x01b    /* RW: Exception save/restore reg 1 */
> > #define SPR_CFAR    0x01c    /* RW: Come From Address Register */
> > +#define SPR_RPR        0x0ba   /* RW: Relative Priority Register */
> > #define SPR_TBRL    0x10c    /* RO: Timebase low */
> > #define SPR_TBRU    0x10d    /* RO: Timebase high */
> > #define SPR_SPRC    0x114    /* RW: Access to uArch SPRs (ex SCOMC)
> > */
> > 
> > 
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