[Skiboot] [RESEND PATCH 01/11]ibm-fsp/firenze: nest data structure definitions
Joel Stanley
joel at jms.id.au
Thu Jul 16 11:57:01 AEST 2015
Hello,
On Sun, 2015-07-05 at 22:25 +0530, Madhavan Srinivasan wrote:
> diff --git a/include/nest.h b/include/nest.h
> new file mode 100644
> index 0000000..0dcd946
> --- /dev/null
> +++ b/include/nest.h
> +/*
> + * Power8 has Nest Instrumentation support with which per-chip
> + * utilisation metrics like memory bandwidth, Xlink/Alink bandwidth and
> + * many other component metrics can be obtained. These Nest
> + * counters can be programmed via scoms or HW PORE Engine,
> + * called PORE_SLW_IMA.
> + *
> + * PORE_SLW_IMA:
> + * PORE_SLW_IMA is a firmware that runs on PORE Engine.
> + * This firmware programs the nest counter and moves counter values to
> + * per chip HOMER region in a fixed offset for each unit. Engine
> + * has a control block structure for communication with Hyperviosr.
Where you say hypervisor, are you referring to skiboot? If so, perhaps
write skiboot.
> + */
> +
> +/*
> + * Control Block structure offset in HOMER IMA Region
> + */
> +#define CB_STRUCT_OFFSET 0x39FC00
> +#define CB_STRUCT_CMD 0x39FC08
> +#define CB_STRUCT_SPEED 0x39FC10
> +#define SLW_IMA_PAUSE 0x2
> +#define SLW_IMA_RESUME 0x1
> +#define SLW_IMA_NOP 0
> +/*
> + * Control Block Structure:
> + *
> + * Name Producer Consumer Values Desc
> + * IMARunStatus IMA Code Hypervisor 0 Initializing
s/Hypervisor/Skiboot/ in this block as well.
> + * 1 Running
> + * 2 Paused
> + *
> + * IMACommand Hypervisor IMA Code 0 NOP
> + * 1 Resume
> + * 2 Pause
> + * 3 Clear and Restart
> + *
> + * IMACollection Hypervisor IMA Code 0 128us
> + * Speed 1 256us
> + * 2 1ms
> + * 3 4ms
> + * 4 16ms
> + * 5 64ms
> + * 6 256ms
> + * 7 1000ms
> + */
> +struct ima_chip_cb
> +{
> + uint64_t ima_chip_run_status;
> + uint64_t ima_chip_command;
> + uint64_t ima_chip_collection_speed;
> +};
> +
> +/*
> + * PORE_SLW_IMA reserved memory (in HOMER region)
> + */
> +#define SLW_IMA_OFFSET 0x00320000
> +#define SLW_IMA_TOTAL_SIZE 0x80000
> +
> +/*
> + * Counter Storage size (exposed as part of DT)
> + */
> +#define SLW_IMA_SIZE 0x10000
> +
> +/*
> + * PTS Scoms and values
> + */
> +#define IMA_PTS_SCOM 0x00068009
> +#define IMA_PTS_ENABLE 0x00F0000000000000
> +#define IMA_PTS_DISABLE 0x00E0000000000000
> +#define IMA_PTS_START 0x1
> +#define IMA_PTS_STOP 0
> +#define IMA_PTS_ERROR -1
> +
> +/*
> + * Catalogue structures.
> + * Catalogue is a meta data file provided as part of FW lid.
> + * This file contains information about the various events the
> + * HW supports under the "24x7" umbrella. Events are classified under
> + * 3 different Domains.
> + * Domain 1 -- Chip Events (PORE_SLW_IMA)
> + * Domain 2 -- Core Events (24x7 Core IMA)
> + * Domain 3 -- per-Thread PMU Events
> + */
> +
> +struct ima_catalog_page_0 {
> +#define CATALOG_MAGIC 0x32347837 /* "24x7" in ASCII */
> + __be32 magic;
> + __be32 length; /* In 4096 byte pages */
> + __be64 version; /* XXX: arbitrary? what's the meaning/useage/purpose? */
usage
> + __u8 build_time_stamp[16]; /* "YYYYMMDDHHMMSS\0\0" */
> + __u8 reserved2[32];
> + __be16 schema_data_offs; /* in 4096 byte pages */
> + __be16 schema_data_len; /* in 4096 byte pages */
> + __be16 schema_entry_count;
> + __u8 reserved3[2];
> + __be16 event_data_offs;
> + __be16 event_data_len;
> + __be16 event_entry_count;
> + __u8 reserved4[2];
> + __be16 group_data_offs; /* in 4096 byte pages */
> + __be16 group_data_len; /* in 4096 byte pages */
> + __be16 group_entry_count;
> + __u8 reserved5[2];
> + __be16 formula_data_offs; /* in 4096 byte pages */
> + __be16 formula_data_len; /* in 4096 byte pages */
> + __be16 formula_entry_count;
> + __u8 reserved6[2];
> + __be32 core_event_offset;
> + __be32 thread_event_offset;
> + __be32 chip_event_offset;
> + __be32 core_group_offset;
> + __be32 thread_group_offset;
> + __be32 chip_group_offset;
> +} __packed;
> +
> +struct ima_catalogue_group_data {
> + __be16 length; /* in bytes, must be a multiple of 16 */
> + __u8 reserved1[2];
> + /* verified_state, unverified_state, caveat_state, broken_state, ... */
> + __be32 flags;
> + __u8 domain; /* Chip = 1, Core = 2 */
> + __u8 reserved2[1];
> + __be16 event_group_record_start_offs; /* in bytes, must be 8 byte aligned */
> + __be16 event_group_record_len; /* in bytes */
> + /* in bytes, offset from event_group_record */
> + __u8 group_schema_index;
> + __u8 event_count;
> + __be16 event_index[16]; /* in bytes */
> + __be16 group_name_len;
> + __u8 remainder[];
> + /* __u8 event_name[event_name_len - 2]; */
> + /* __be16 event_description_len; */
> + /* __u8 event_desc[event_description_len - 2]; */
> + /* __be16 detailed_desc_len; */
> + /* __u8 detailed_desc[detailed_desc_len - 2]; */
> +} __packed;
> +
> +struct ima_catalogue_event_data {
> + __be16 length; /* in bytes, must be a multiple of 16 */
> + __be16 formula_index;
> + __u8 domain; /* Chip = 1, Core = 2 */
> + __u8 reserved2[1];
> + __be16 event_group_record_offs; /* in bytes, must be 8 byte aligned */
> + __be16 event_group_record_len; /* in bytes */
> +
> + /* in bytes, offset from event_group_record */
> + __be16 event_counter_offs;
> +
> + /* verified_state, unverified_state, caveat_state, broken_state, ... */
> + __be32 flags;
> +
> + __be16 primary_group_ix;
> + __be16 group_count;
> + __be16 event_name_len;
> + __u8 remainder[];
> + /* __u8 event_name[event_name_len - 2]; */
> + /* __be16 event_description_len; */
> + /* __u8 event_desc[event_description_len - 2]; */
> + /* __be16 detailed_desc_len; */
> + /* __u8 detailed_desc[detailed_desc_len - 2]; */
> +} __packed;
> +
> +
> +#define CHIP_EVENTS_SUPPORTED 1
> +#define CHIP_EVENTS_NOT_SUPPORTED 0
> +
> +/*
> + * Just for optimisation, save only relavent addrs
relevant
> + */
> +struct page0_offsets {
> + char *page0;
> + char *group_entry;
> + char *event_entry;
> + char *thread_event_entry;
> + char *core_event_entry;
> + char *chip_event_entry;
> + char *thread_group_entry;
> + char *core_group_entry;
> + char *chip_group_entry;
> +};
> +
> +#define PAGE0(x) x->page0
> +#define GROUP_ENTRY(x) x->group_entry
> +#define EVENT_ENTRY(x) x->event_entry
> +#define THREAD_EVENT_ENTRY(x) x->thread_event_entry
> +#define CORE_EVENT_ENTRY(x) x->core_event_entry
> +#define CHIP_EVENT_ENTRY(x) x->chip_event_entry
> +#define THREAD_GROUP_ENTRY(x) x->thread_group_entry
> +#define CORE_GROUP_ENTRY(x) x->core_group_entry
> +#define CHIP_GROUP_ENTRY(x) x->chip_group_entry
> +
> +/* Event Domains, Chip=1, Core=2 */
> +#define DOMAIN_CHIP 1
> +#define DOMAIN_CORE 2
> +
> +/* dimm information for utilssation metrics */
utilisation
> +#define MURANO_CENTAUR_DIMM 24000
> +#define VENICE_CENTAUR_DIMM 27000
> +
> +#endif /* __NEST_H__ */
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