[Skiboot] [PATCH v2 12/12] opal: Recover from TOD register parity errors.

[Stewart Smith]

Mahesh Jagannath Salgaonkar <mahesh at linux.vnet.ibm.com> writes:
>> which makse sense when you look at skiboot log:
>> [41797933478,6] CHIPTOD: Calculated MCBS is 0x4b (Cfreq=4024000000 Tfreq=320000
>> 00).
>> [41797936890,7] CHIPTOD: Base TFMR=0x4b12000000000000.
>> [41796320335,7] CHIPTOD: Master sync on CPU PIR 0x0048....
>> [41801786711,7] CHIPTOD: Slave sync on CPU PIR 0x0058....
>> [41809523634,7] CHIPTOD: Slave sync on CPU PIR 0x0068....
>> [7309025,7] CHIPTOD: PIR 0x0048 TB=6f86cc.
>> [7313179,7] CHIPTOD: PIR 0x0058 TB=6f9707.
>> [7680789,7] CHIPTOD: PIR 0x0068 TB=753300.
>> [7689063,7] CHIPTOD: TOD Topology in Use: Primary.
>> [7691343,7] CHIPTOD:   Primary configuration:.
>> [7693122,7] CHIPTOD:    chip id: 0, Role: MDMT, Status: Active Master.
>> [7696585,7] CHIPTOD:   Secondary configuration:.
>> [7698434,7] CHIPTOD:    chip id: 0, Role: MDMT, Status: Active Master.
>
> Palmetto is single chip system. It looks like It is wrongly informing
> same chip id as secondary to opal through device tree. Ideally we should
> have seen chip id as -1 for secondary configuration.
>
> Let get grab palmetto if I can and verify all this.

cool. I haven't checked the code, but it sounds more ideal if we just
crash quickly and cleanly in this situation.