[Skiboot] [PATCH 1/2] hw/phb3: Change reserved PE to 255

Stewart Smith stewart at linux.vnet.ibm.com
Fri Aug 14 14:11:24 AEST 2015

Gavin Shan <gwshan at linux.vnet.ibm.com> writes:
> Currently, we have reserved PE#0 to which all RIDs are mapped prior
> to PE assignment request from kernel. The last M64 BAR is configured
> to have shared mode. So we have to cut off the first M64 segment,
> which corresponds to reserved PE#0 in kernel. If the first BAR
> (for example PF's IOV BAR) requires huge alignment in kernel, we
> have to waste huge M64 space to accomodate the alignment. If we
> have reserved PE#256, the waste of M64 space will be avoided.
> Signed-off-by: Gavin Shan <gwshan at linux.vnet.ibm.com>

thanks, merged as 9af2d0b1b

More information about the Skiboot mailing list