[Skiboot-stable] [PATCH] phb4: Disable TCE cache line buffer

[Frederic Barrat]

This patch implements a circumvention for HW557787. It disables the
TCE cache line buffer as, under heavy loads, there's a possibility of
an entry being re-allocated incorrectly.

Signed-off-by: Frederic Barrat <fbarrat at linux.ibm.com>
---
 hw/phb4.c           | 1 +
 include/phb4-regs.h | 1 +
 2 files changed, 2 insertions(+)

diff --git a/hw/phb4.c b/hw/phb4.c
index e7758d34..6788abd2 100644
--- a/hw/phb4.c
+++ b/hw/phb4.c
@@ -5303,6 +5303,7 @@ static void phb4_init_hw(struct phb4 *p)
 
 	/* Init_17 - PHB Control */
 	val = PHB_CTRLR_IRQ_PGSZ_64K;
+	val |= PHB_CTRLR_TCE_CLB_DISABLE; // HW557787 circumvention
 	val |= SETFIELD(PHB_CTRLR_TVT_ADDR_SEL, 0ull, TVT_2_PER_PE);
 	if (PHB4_CAN_STORE_EOI(p))
 		val |= PHB_CTRLR_IRQ_STORE_EOI;
diff --git a/include/phb4-regs.h b/include/phb4-regs.h
index d3b0aac4..b6e77874 100644
--- a/include/phb4-regs.h
+++ b/include/phb4-regs.h
@@ -110,6 +110,7 @@
 #define     TVT_4_PER_PE		1
 #define     TVT_8_PER_PE		2
 #define     TVT_16_PER_PE		3
+#define   PHB_CTRLR_TCE_CLB_DISABLE	PPC_BIT(21)
 #define   PHB_CTRLR_DMA_RD_SPACING	PPC_BITMASK(28,31)
 #define PHB_AIB_FENCE_CTRL		0x860
 #define PHB_TCE_TAG_ENABLE		0x868
-- 
2.26.2