[Skiboot-stable] [Skiboot] [PATCH 1/2] mowgli: Limit slot1 to Gen3 by default

[Vasant Hegde]

On 11/9/20 10:06 PM, Frederic Barrat wrote:
> 
> 
> On 30/10/2020 03:22, Lulu Su wrote:
>> From: LuluTHSu<Lulu_Su at wistron.com>
>>
>> Refer to the spec. of mowgli, limit the slot to Gen3 speed.
>> For mowgli platform spec.
>>
>> Cc:skiboot-stable at lists.ozlabs.org
>> Signed-off-by: LuluTHSu<Lulu_Su at wistron.com>
>> ---
>>   hw/phb4.c                 | 21 +++++++++++++++++++++
>>   include/phb4.h            |  1 +
>>   platforms/astbmc/mowgli.c | 16 ++++++++++++++++
>>   3 files changed, 38 insertions(+)
>>
>> diff --git a/hw/phb4.c b/hw/phb4.c
>> index 17a233f..de10bb0 100644
>> --- a/hw/phb4.c
>> +++ b/hw/phb4.c
>> @@ -2991,6 +2991,27 @@ static unsigned int phb4_get_max_link_speed(struct phb4 
>> *p, struct dt_node *np)
>>       return max_link_speed;
>>   }
>> +/*
>> + * Has the same effect as the ibm,max-link-speed property.
>> + * i.e. sets the default link speed, while allowing NVRAM
>> + * overrides, etc to still take effect.
>> + */
>> +void phb4_set_dt_max_link_speed(struct phb4 *p, int new_max)
>> +{
>> +    uint64_t scr;
>> +    int max;
>> +
>> +    /* take into account nvram settings, etc */
>> +    if (pcie_max_link_speed)
>> +        max = pcie_max_link_speed;
>> +    else
>> +        max = new_max;
>> +
>> +    scr = phb4_read_reg(p, PHB_PCIE_SCR);
>> +    scr = SETFIELD(PHB_PCIE_SCR_MAXLINKSPEED, scr, max);
>> +    phb4_write_reg(p, PHB_PCIE_SCR, scr);
>> +}
>> +
> 
> 
> This patch has already been merged, but I think there's a problem here. This 
> should work to limit the link speed at boot, when the link is trained for the 
> first time. However, since we're writing directly in the register, skiboot won't 
> memorize the limit and on the next link reset/retrain (due to a EEH recovery or 
> PCI hotplug for example), then that is lost. And mowgli_setup_phb() won't be 
> called either on that path.


Lulu,

Can you guys fix this issue?

-Vasant