[Pdbg] [PATCH] P8 ADU: Fix access sizes

[Alistair Popple]

Commit 302f249d95f0 ("adu: Add arugments for block size") introduced
the ability to specify an access size for the POWER8 and POWER9 ADU
functions for cache-inhibited access.

On POWER8 the ADU control register TSIZE encoding is slightly
different than for POWER9. Unfortunately the code for P8 was copied
from the P9 version but the encoding was not updated. This resulted in
ADU putmem commands writing twice as much memory as they were supposed
to on POWER8.

Signed-off-by: Alistair Popple <alistair at popple.id.au>
---
 libpdbg/adu.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/libpdbg/adu.c b/libpdbg/adu.c
index 25f08cd..df610a7 100644
--- a/libpdbg/adu.c
+++ b/libpdbg/adu.c
@@ -344,7 +344,7 @@ static int p8_adu_getmem(struct mem *adu, uint64_t addr, uint64_t *data,
 	if (ci) {
 		/* Do cache inhibited access */
 		ctrl_reg = SETFIELD(P8_FBC_ALTD_TTYPE, ctrl_reg, P8_TTYPE_CI_PARTIAL_READ);
-		block_size = (blog2(block_size) + 1) << 1;
+		block_size = (blog2(block_size) + 1);
 	} else {
 		ctrl_reg = SETFIELD(P8_FBC_ALTD_TTYPE, ctrl_reg, P8_TTYPE_DMA_PARTIAL_READ);
 		block_size = 0;
@@ -405,10 +405,9 @@ int p8_adu_putmem(struct mem *adu, uint64_t addr, uint64_t data, int size,
 	if (ci) {
 		/* Do cache inhibited access */
 		ctrl_reg = SETFIELD(P8_FBC_ALTD_TTYPE, ctrl_reg, P8_TTYPE_CI_PARTIAL_WRITE);
-		block_size = (blog2(block_size) + 1) << 1;
+		block_size = (blog2(block_size) + 1);
 	} else {
 		ctrl_reg = SETFIELD(P8_FBC_ALTD_TTYPE, ctrl_reg, P8_TTYPE_DMA_PARTIAL_WRITE);
-		block_size <<= 1;
 	}
 	ctrl_reg = SETFIELD(P8_FBC_ALTD_TSIZE, ctrl_reg, block_size);
 
-- 
2.20.1