[Pdbg] [RFC PATCH 01/11] dts: Add full expanded p9 device tree
Amitay Isaacs
amitay at ozlabs.org
Tue Nov 12 13:12:41 AEDT 2019
Signed-off-by: Amitay Isaacs <amitay at ozlabs.org>
---
p9.dts | 2826 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 2826 insertions(+)
create mode 100644 p9.dts
diff --git a/p9.dts b/p9.dts
new file mode 100644
index 0000000..a6f402b
--- /dev/null
+++ b/p9.dts
@@ -0,0 +1,2826 @@
+/dts-v1/;
+
+/ {
+
+ mem0 {
+ index = < 0x00 >;
+ };
+
+ proc0 {
+ index = < 0x00 >;
+
+ fsi {
+ index = < 0x00 >;
+ };
+
+ pib {
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+ index = < 0x00 >;
+
+ adu at 90000 {
+ compatible = "ibm-power9-adu";
+ reg = < 0x00 0x90000 0x50 >;
+ system-path = "/mem0";
+ };
+
+ htm at 5012880 {
+ compatible = "ibm,power9-nhtm";
+ reg = < 0x00 0x5012880 0x40 >;
+ index = < 0x00 >;
+ };
+
+ htm at 50128C0 {
+ compatible = "ibm,power9-nhtm";
+ reg = < 0x00 0x50128c0 0x40 >;
+ index = < 0x01 >;
+ };
+
+ chiplet at 1000000 {
+ compatible = "ibm,power9-chiplet";
+ index = < 0x01 >;
+ reg = < 0x00 0x1000000 0xfffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ tp at 0 {
+ compatible = "ibm,power9-tp";
+ index = < 0x00 >;
+ reg = < 0x00 0x1000000 0xffffff >;
+ };
+ };
+
+ chiplet at 2000000 {
+ compatible = "ibm,power9-chiplet";
+ index = < 0x02 >;
+ reg = < 0x00 0x2000000 0xfffff >;
+ };
+
+ chiplet at 3000000 {
+ compatible = "ibm,power9-chiplet";
+ index = < 0x03 >;
+ reg = < 0x00 0x3000000 0xfffff >;
+ };
+
+ chiplet at 4000000 {
+ compatible = "ibm,power9-chiplet";
+ index = < 0x04 >;
+ reg = < 0x00 0x4000000 0xfffff >;
+ };
+
+ chiplet at 5000000 {
+ compatible = "ibm,power9-chiplet";
+ index = < 0x05 >;
+ reg = < 0x00 0x5000000 0xfffff >;
+ };
+
+ chiplet at 6000000 {
+ compatible = "ibm,power9-chiplet";
+ index = < 0x06 >;
+ reg = < 0x00 0x6000000 0xfffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ xbus0_0: xbus at 0 {
+ compatible = "ibm,power9-xbus";
+ index = < 0x00 >;
+ reg = < 0x00 0x6000000 0xffffff >;
+ other-end = "/proc1/pib/chiplet at 6000000/xbus at 0";
+ };
+ };
+
+ chiplet at 7000000 {
+ compatible = "ibm,power9-chiplet";
+ index = < 0x07 >;
+ reg = < 0x00 0x7000000 0xfffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ mc at 0 {
+ compatible = "ibm,power9-mc";
+ index = < 0x00 >;
+ reg = < 0x00 0x7000000 0xffffff >;
+ };
+ };
+
+ chiplet at 8000000 {
+ compatible = "ibm,power9-chiplet";
+ index = < 0x08 >;
+ reg = < 0x00 0x8000000 0xfffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ mc at 1 {
+ compatible = "ibm,power9-mc";
+ index = < 0x01 >;
+ reg = < 0x00 0x8000000 0xffffff >;
+ };
+ };
+
+ chiplet at 9000000 {
+ compatible = "ibm,power9-chiplet";
+ index = < 0x09 >;
+ reg = < 0x00 0x9000000 0xfffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ obus at 0 {
+ compatible = "ibm,power9-obus";
+ index = < 0x00 >;
+ reg = < 0x00 0x9000000 0xffffff >;
+ };
+ };
+
+ chiplet at c000000 {
+ compatible = "ibm,power9-chiplet";
+ index = < 0x0c >;
+ reg = < 0x00 0xc000000 0xfffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ obus at 3 {
+ compatible = "ibm,power9-obus";
+ index = < 0x03 >;
+ reg = < 0x00 0xc000000 0xffffff >;
+ };
+ };
+
+ chiplet at d000000 {
+ compatible = "ibm,power9-chiplet";
+ index = < 0x0d >;
+ reg = < 0x00 0xd000000 0xfffff >;
+ };
+
+ chiplet at e000000 {
+ compatible = "ibm,power9-chiplet";
+ index = < 0x0e >;
+ reg = < 0x00 0xe000000 0xfffff >;
+ };
+
+ chiplet at f000000 {
+ compatible = "ibm,power9-chiplet";
+ index = < 0x0f >;
+ reg = < 0x00 0xf000000 0xfffff >;
+ };
+
+ chiplet at 10000000 {
+ compatible = "ibm,power9-chiplet";
+ index = < 0x10 >;
+ reg = < 0x00 0x10000000 0xfffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ eq at 0 {
+ compatible = "ibm,power9-eq";
+ index = < 0x00 >;
+ reg = < 0x00 0x10000000 0xffffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ ex at 0 {
+ compatible = "ibm,power9-ex";
+ index = < 0x00 >;
+ reg = < 0x00 0x10000000 0xffffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ chiplet at 20000000 {
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+ compatible = "ibm,power9-chiplet";
+ index = < 0x20 >;
+ reg = < 0x00 0x20000000 0xfffff >;
+
+ core at 0 {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x00 >;
+ compatible = "ibm,power9-core";
+ index = < 0x00 >;
+ reg = < 0x00 0x00 0xfffff >;
+
+ thread at 0 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x00 >;
+ index = < 0x00 >;
+ };
+
+ thread at 1 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x01 >;
+ index = < 0x01 >;
+ };
+
+ thread at 2 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x02 >;
+ index = < 0x02 >;
+ };
+
+ thread at 3 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x03 >;
+ index = < 0x03 >;
+ };
+ };
+ };
+
+ chiplet at 21000000 {
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+ compatible = "ibm,power9-chiplet";
+ index = < 0x21 >;
+ reg = < 0x00 0x21000000 0xfffff >;
+
+ core at 0 {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x00 >;
+ compatible = "ibm,power9-core";
+ index = < 0x01 >;
+ reg = < 0x00 0x00 0xfffff >;
+
+ thread at 0 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x00 >;
+ index = < 0x00 >;
+ };
+
+ thread at 1 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x01 >;
+ index = < 0x01 >;
+ };
+
+ thread at 2 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x02 >;
+ index = < 0x02 >;
+ };
+
+ thread at 3 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x03 >;
+ index = < 0x03 >;
+ };
+ };
+ };
+ };
+
+ ex at 1 {
+ compatible = "ibm,power9-ex";
+ index = < 0x01 >;
+ reg = < 0x00 0x10000000 0xffffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ chiplet at 22000000 {
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+ compatible = "ibm,power9-chiplet";
+ index = < 0x22 >;
+ reg = < 0x00 0x22000000 0xfffff >;
+
+ core at 0 {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x00 >;
+ compatible = "ibm,power9-core";
+ index = < 0x02 >;
+ reg = < 0x00 0x00 0xfffff >;
+
+ thread at 0 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x00 >;
+ index = < 0x00 >;
+ };
+
+ thread at 1 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x01 >;
+ index = < 0x01 >;
+ };
+
+ thread at 2 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x02 >;
+ index = < 0x02 >;
+ };
+
+ thread at 3 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x03 >;
+ index = < 0x03 >;
+ };
+ };
+ };
+
+ chiplet at 23000000 {
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+ compatible = "ibm,power9-chiplet";
+ index = < 0x23 >;
+ reg = < 0x00 0x23000000 0xfffff >;
+
+ core at 0 {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x00 >;
+ compatible = "ibm,power9-core";
+ index = < 0x03 >;
+ reg = < 0x00 0x00 0xfffff >;
+
+ thread at 0 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x00 >;
+ index = < 0x00 >;
+ };
+
+ thread at 1 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x01 >;
+ index = < 0x01 >;
+ };
+
+ thread at 2 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x02 >;
+ index = < 0x02 >;
+ };
+
+ thread at 3 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x03 >;
+ index = < 0x03 >;
+ };
+ };
+ };
+ };
+ };
+ };
+
+ chiplet at 11000000 {
+ compatible = "ibm,power9-chiplet";
+ index = < 0x11 >;
+ reg = < 0x00 0x11000000 0xfffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ eq at 1 {
+ compatible = "ibm,power9-eq";
+ index = < 0x01 >;
+ reg = < 0x00 0x11000000 0xffffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ ex at 0 {
+ compatible = "ibm,power9-ex";
+ index = < 0x00 >;
+ reg = < 0x00 0x10000000 0xffffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ chiplet at 24000000 {
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+ compatible = "ibm,power9-chiplet";
+ index = < 0x24 >;
+ reg = < 0x00 0x24000000 0xfffff >;
+
+ core at 0 {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x00 >;
+ compatible = "ibm,power9-core";
+ index = < 0x04 >;
+ reg = < 0x00 0x00 0xfffff >;
+
+ thread at 0 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x00 >;
+ index = < 0x00 >;
+ };
+
+ thread at 1 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x01 >;
+ index = < 0x01 >;
+ };
+
+ thread at 2 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x02 >;
+ index = < 0x02 >;
+ };
+
+ thread at 3 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x03 >;
+ index = < 0x03 >;
+ };
+ };
+ };
+
+ chiplet at 25000000 {
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+ compatible = "ibm,power9-chiplet";
+ index = < 0x25 >;
+ reg = < 0x00 0x25000000 0xfffff >;
+
+ core at 0 {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x00 >;
+ compatible = "ibm,power9-core";
+ index = < 0x05 >;
+ reg = < 0x00 0x00 0xfffff >;
+
+ thread at 0 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x00 >;
+ index = < 0x00 >;
+ };
+
+ thread at 1 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x01 >;
+ index = < 0x01 >;
+ };
+
+ thread at 2 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x02 >;
+ index = < 0x02 >;
+ };
+
+ thread at 3 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x03 >;
+ index = < 0x03 >;
+ };
+ };
+ };
+ };
+
+ ex at 1 {
+ compatible = "ibm,power9-ex";
+ index = < 0x01 >;
+ reg = < 0x00 0x10000000 0xffffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ chiplet at 26000000 {
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+ compatible = "ibm,power9-chiplet";
+ index = < 0x26 >;
+ reg = < 0x00 0x26000000 0xfffff >;
+
+ core at 0 {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x00 >;
+ compatible = "ibm,power9-core";
+ index = < 0x06 >;
+ reg = < 0x00 0x00 0xfffff >;
+
+ thread at 0 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x00 >;
+ index = < 0x00 >;
+ };
+
+ thread at 1 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x01 >;
+ index = < 0x01 >;
+ };
+
+ thread at 2 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x02 >;
+ index = < 0x02 >;
+ };
+
+ thread at 3 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x03 >;
+ index = < 0x03 >;
+ };
+ };
+ };
+
+ chiplet at 27000000 {
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+ compatible = "ibm,power9-chiplet";
+ index = < 0x27 >;
+ reg = < 0x00 0x27000000 0xfffff >;
+
+ core at 0 {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x00 >;
+ compatible = "ibm,power9-core";
+ index = < 0x07 >;
+ reg = < 0x00 0x00 0xfffff >;
+
+ thread at 0 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x00 >;
+ index = < 0x00 >;
+ };
+
+ thread at 1 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x01 >;
+ index = < 0x01 >;
+ };
+
+ thread at 2 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x02 >;
+ index = < 0x02 >;
+ };
+
+ thread at 3 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x03 >;
+ index = < 0x03 >;
+ };
+ };
+ };
+ };
+ };
+ };
+
+ chiplet at 12000000 {
+ compatible = "ibm,power9-chiplet";
+ index = < 0x12 >;
+ reg = < 0x00 0x12000000 0xfffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ eq at 2 {
+ compatible = "ibm,power9-eq";
+ index = < 0x02 >;
+ reg = < 0x00 0x12000000 0xffffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ ex at 0 {
+ compatible = "ibm,power9-ex";
+ index = < 0x00 >;
+ reg = < 0x00 0x12000000 0xffffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ chiplet at 28000000 {
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+ compatible = "ibm,power9-chiplet";
+ index = < 0x28 >;
+ reg = < 0x00 0x28000000 0xfffff >;
+
+ core at 0 {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x00 >;
+ compatible = "ibm,power9-core";
+ index = < 0x08 >;
+ reg = < 0x00 0x00 0xfffff >;
+
+ thread at 0 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x00 >;
+ index = < 0x00 >;
+ };
+
+ thread at 1 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x01 >;
+ index = < 0x01 >;
+ };
+
+ thread at 2 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x02 >;
+ index = < 0x02 >;
+ };
+
+ thread at 3 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x03 >;
+ index = < 0x03 >;
+ };
+ };
+ };
+
+ chiplet at 29000000 {
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+ compatible = "ibm,power9-chiplet";
+ index = < 0x29 >;
+ reg = < 0x00 0x29000000 0xfffff >;
+
+ core at 0 {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x00 >;
+ compatible = "ibm,power9-core";
+ index = < 0x09 >;
+ reg = < 0x00 0x00 0xfffff >;
+
+ thread at 0 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x00 >;
+ index = < 0x00 >;
+ };
+
+ thread at 1 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x01 >;
+ index = < 0x01 >;
+ };
+
+ thread at 2 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x02 >;
+ index = < 0x02 >;
+ };
+
+ thread at 3 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x03 >;
+ index = < 0x03 >;
+ };
+ };
+ };
+ };
+
+ ex at 1 {
+ compatible = "ibm,power9-ex";
+ index = < 0x01 >;
+ reg = < 0x00 0x12000000 0xffffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ chiplet at 2a000000 {
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+ compatible = "ibm,power9-chiplet";
+ index = < 0x2a >;
+ reg = < 0x00 0x2a000000 0xfffff >;
+
+ core at 0 {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x00 >;
+ compatible = "ibm,power9-core";
+ index = < 0x0a >;
+ reg = < 0x00 0x00 0xfffff >;
+
+ thread at 0 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x00 >;
+ index = < 0x00 >;
+ };
+
+ thread at 1 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x01 >;
+ index = < 0x01 >;
+ };
+
+ thread at 2 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x02 >;
+ index = < 0x02 >;
+ };
+
+ thread at 3 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x03 >;
+ index = < 0x03 >;
+ };
+ };
+ };
+
+ chiplet at 2b000000 {
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+ compatible = "ibm,power9-chiplet";
+ index = < 0x2b >;
+ reg = < 0x00 0x2b000000 0xfffff >;
+
+ core at 0 {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x00 >;
+ compatible = "ibm,power9-core";
+ index = < 0x0b >;
+ reg = < 0x00 0x00 0xfffff >;
+
+ thread at 0 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x00 >;
+ index = < 0x00 >;
+ };
+
+ thread at 1 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x01 >;
+ index = < 0x01 >;
+ };
+
+ thread at 2 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x02 >;
+ index = < 0x02 >;
+ };
+
+ thread at 3 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x03 >;
+ index = < 0x03 >;
+ };
+ };
+ };
+ };
+ };
+ };
+
+ chiplet at 13000000 {
+ compatible = "ibm,power9-chiplet";
+ index = < 0x13 >;
+ reg = < 0x00 0x13000000 0xfffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ eq at 3 {
+ compatible = "ibm,power9-eq";
+ index = < 0x03 >;
+ reg = < 0x00 0x13000000 0xffffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ ex at 0 {
+ compatible = "ibm,power9-ex";
+ index = < 0x00 >;
+ reg = < 0x00 0x13000000 0xffffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ chiplet at 2c000000 {
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+ compatible = "ibm,power9-chiplet";
+ index = < 0x2c >;
+ reg = < 0x00 0x2c000000 0xfffff >;
+
+ core at 0 {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x00 >;
+ compatible = "ibm,power9-core";
+ index = < 0x0c >;
+ reg = < 0x00 0x00 0xfffff >;
+
+ thread at 0 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x00 >;
+ index = < 0x00 >;
+ };
+
+ thread at 1 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x01 >;
+ index = < 0x01 >;
+ };
+
+ thread at 2 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x02 >;
+ index = < 0x02 >;
+ };
+
+ thread at 3 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x03 >;
+ index = < 0x03 >;
+ };
+ };
+ };
+
+ chiplet at 2d000000 {
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+ compatible = "ibm,power9-chiplet";
+ index = < 0x2d >;
+ reg = < 0x00 0x2d000000 0xfffff >;
+
+ core at 0 {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x00 >;
+ compatible = "ibm,power9-core";
+ index = < 0x0d >;
+ reg = < 0x00 0x00 0xfffff >;
+
+ thread at 0 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x00 >;
+ index = < 0x00 >;
+ };
+
+ thread at 1 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x01 >;
+ index = < 0x01 >;
+ };
+
+ thread at 2 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x02 >;
+ index = < 0x02 >;
+ };
+
+ thread at 3 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x03 >;
+ index = < 0x03 >;
+ };
+ };
+ };
+ };
+
+ ex at 1 {
+ compatible = "ibm,power9-ex";
+ index = < 0x01 >;
+ reg = < 0x00 0x13000000 0xffffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ chiplet at 2e000000 {
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+ compatible = "ibm,power9-chiplet";
+ index = < 0x2e >;
+ reg = < 0x00 0x2e000000 0xfffff >;
+
+ core at 0 {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x00 >;
+ compatible = "ibm,power9-core";
+ index = < 0x0e >;
+ reg = < 0x00 0x00 0xfffff >;
+
+ thread at 0 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x00 >;
+ index = < 0x00 >;
+ };
+
+ thread at 1 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x01 >;
+ index = < 0x01 >;
+ };
+
+ thread at 2 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x02 >;
+ index = < 0x02 >;
+ };
+
+ thread at 3 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x03 >;
+ index = < 0x03 >;
+ };
+ };
+ };
+
+ chiplet at 2f000000 {
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+ compatible = "ibm,power9-chiplet";
+ index = < 0x2f >;
+ reg = < 0x00 0x2f000000 0xfffff >;
+
+ core at 0 {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x00 >;
+ compatible = "ibm,power9-core";
+ index = < 0x0f >;
+ reg = < 0x00 0x00 0xfffff >;
+
+ thread at 0 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x00 >;
+ index = < 0x00 >;
+ };
+
+ thread at 1 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x01 >;
+ index = < 0x01 >;
+ };
+
+ thread at 2 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x02 >;
+ index = < 0x02 >;
+ };
+
+ thread at 3 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x03 >;
+ index = < 0x03 >;
+ };
+ };
+ };
+ };
+ };
+ };
+
+ chiplet at 14000000 {
+ compatible = "ibm,power9-chiplet";
+ index = < 0x14 >;
+ reg = < 0x00 0x14000000 0xfffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ eq at 4 {
+ compatible = "ibm,power9-eq";
+ index = < 0x04 >;
+ reg = < 0x00 0x13000000 0xffffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ ex at 0 {
+ compatible = "ibm,power9-ex";
+ index = < 0x00 >;
+ reg = < 0x00 0x14000000 0xffffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ chiplet at 30000000 {
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+ compatible = "ibm,power9-chiplet";
+ index = < 0x30 >;
+ reg = < 0x00 0x30000000 0xfffff >;
+
+ core at 0 {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x00 >;
+ compatible = "ibm,power9-core";
+ index = < 0x10 >;
+ reg = < 0x00 0x00 0xfffff >;
+
+ thread at 0 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x00 >;
+ index = < 0x00 >;
+ };
+
+ thread at 1 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x01 >;
+ index = < 0x01 >;
+ };
+
+ thread at 2 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x02 >;
+ index = < 0x02 >;
+ };
+
+ thread at 3 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x03 >;
+ index = < 0x03 >;
+ };
+ };
+ };
+
+ chiplet at 31000000 {
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+ compatible = "ibm,power9-chiplet";
+ index = < 0x31 >;
+ reg = < 0x00 0x31000000 0xfffff >;
+
+ core at 0 {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x00 >;
+ compatible = "ibm,power9-core";
+ index = < 0x11 >;
+ reg = < 0x00 0x00 0xfffff >;
+
+ thread at 0 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x00 >;
+ index = < 0x00 >;
+ };
+
+ thread at 1 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x01 >;
+ index = < 0x01 >;
+ };
+
+ thread at 2 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x02 >;
+ index = < 0x02 >;
+ };
+
+ thread at 3 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x03 >;
+ index = < 0x03 >;
+ };
+ };
+ };
+ };
+
+ ex at 1 {
+ compatible = "ibm,power9-ex";
+ index = < 0x01 >;
+ reg = < 0x00 0x14000000 0xffffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ chiplet at 32000000 {
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+ compatible = "ibm,power9-chiplet";
+ index = < 0x32 >;
+ reg = < 0x00 0x32000000 0xfffff >;
+
+ core at 0 {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x00 >;
+ compatible = "ibm,power9-core";
+ index = < 0x12 >;
+ reg = < 0x00 0x00 0xfffff >;
+
+ thread at 0 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x00 >;
+ index = < 0x00 >;
+ };
+
+ thread at 1 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x01 >;
+ index = < 0x01 >;
+ };
+
+ thread at 2 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x02 >;
+ index = < 0x02 >;
+ };
+
+ thread at 3 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x03 >;
+ index = < 0x03 >;
+ };
+ };
+ };
+
+ chiplet at 33000000 {
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+ compatible = "ibm,power9-chiplet";
+ index = < 0x33 >;
+ reg = < 0x00 0x33000000 0xfffff >;
+
+ core at 0 {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x00 >;
+ compatible = "ibm,power9-core";
+ index = < 0x13 >;
+ reg = < 0x00 0x00 0xfffff >;
+
+ thread at 0 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x00 >;
+ index = < 0x00 >;
+ };
+
+ thread at 1 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x01 >;
+ index = < 0x01 >;
+ };
+
+ thread at 2 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x02 >;
+ index = < 0x02 >;
+ };
+
+ thread at 3 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x03 >;
+ index = < 0x03 >;
+ };
+ };
+ };
+ };
+ };
+ };
+
+ chiplet at 15000000 {
+ compatible = "ibm,power9-chiplet";
+ index = < 0x15 >;
+ reg = < 0x00 0x15000000 0xfffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ eq at 5 {
+ compatible = "ibm,power9-eq";
+ index = < 0x05 >;
+ reg = < 0x00 0x13000000 0xffffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ ex at 0 {
+ compatible = "ibm,power9-ex";
+ index = < 0x00 >;
+ reg = < 0x00 0x15000000 0xffffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ chiplet at 34000000 {
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+ compatible = "ibm,power9-chiplet";
+ index = < 0x34 >;
+ reg = < 0x00 0x34000000 0xfffff >;
+
+ core at 0 {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x00 >;
+ compatible = "ibm,power9-core";
+ index = < 0x14 >;
+ reg = < 0x00 0x00 0xfffff >;
+
+ thread at 0 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x00 >;
+ index = < 0x00 >;
+ };
+
+ thread at 1 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x01 >;
+ index = < 0x01 >;
+ };
+
+ thread at 2 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x02 >;
+ index = < 0x02 >;
+ };
+
+ thread at 3 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x03 >;
+ index = < 0x03 >;
+ };
+ };
+ };
+
+ chiplet at 35000000 {
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+ compatible = "ibm,power9-chiplet";
+ index = < 0x35 >;
+ reg = < 0x00 0x35000000 0xfffff >;
+
+ core at 0 {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x00 >;
+ compatible = "ibm,power9-core";
+ index = < 0x15 >;
+ reg = < 0x00 0x00 0xfffff >;
+
+ thread at 0 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x00 >;
+ index = < 0x00 >;
+ };
+
+ thread at 1 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x01 >;
+ index = < 0x01 >;
+ };
+
+ thread at 2 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x02 >;
+ index = < 0x02 >;
+ };
+
+ thread at 3 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x03 >;
+ index = < 0x03 >;
+ };
+ };
+ };
+ };
+
+ ex at 1 {
+ compatible = "ibm,power9-ex";
+ index = < 0x01 >;
+ reg = < 0x00 0x15000000 0xffffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ chiplet at 36000000 {
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+ compatible = "ibm,power9-chiplet";
+ index = < 0x36 >;
+ reg = < 0x00 0x36000000 0xfffff >;
+
+ core at 0 {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x00 >;
+ compatible = "ibm,power9-core";
+ index = < 0x16 >;
+ reg = < 0x00 0x00 0xfffff >;
+
+ thread at 0 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x00 >;
+ index = < 0x00 >;
+ };
+
+ thread at 1 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x01 >;
+ index = < 0x01 >;
+ };
+
+ thread at 2 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x02 >;
+ index = < 0x02 >;
+ };
+
+ thread at 3 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x03 >;
+ index = < 0x03 >;
+ };
+ };
+ };
+
+ chiplet at 37000000 {
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+ compatible = "ibm,power9-chiplet";
+ index = < 0x37 >;
+ reg = < 0x00 0x37000000 0xfffff >;
+
+ core at 0 {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x00 >;
+ compatible = "ibm,power9-core";
+ index = < 0x17 >;
+ reg = < 0x00 0x00 0xfffff >;
+
+ thread at 0 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x00 >;
+ index = < 0x00 >;
+ };
+
+ thread at 1 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x01 >;
+ index = < 0x01 >;
+ };
+
+ thread at 2 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x02 >;
+ index = < 0x02 >;
+ };
+
+ thread at 3 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x03 >;
+ index = < 0x03 >;
+ };
+ };
+ };
+ };
+ };
+ };
+ };
+ };
+
+ mem1 {
+ index = < 0x01 >;
+ };
+
+ proc1 {
+ index = < 0x01 >;
+
+ fsi {
+ index = < 0x00 >;
+ };
+
+ pib {
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+ index = < 0x00 >;
+
+ adu at 90000 {
+ compatible = "ibm-power9-adu";
+ reg = < 0x00 0x90000 0x50 >;
+ system-path = "/mem1";
+ };
+
+ htm at 5012880 {
+ compatible = "ibm,power9-nhtm";
+ reg = < 0x00 0x5012880 0x40 >;
+ index = < 0x00 >;
+ };
+
+ htm at 50128C0 {
+ compatible = "ibm,power9-nhtm";
+ reg = < 0x00 0x50128c0 0x40 >;
+ index = < 0x01 >;
+ };
+
+ chiplet at 1000000 {
+ compatible = "ibm,power9-chiplet";
+ index = < 0x01 >;
+ reg = < 0x00 0x1000000 0xfffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ tp at 0 {
+ compatible = "ibm,power9-tp";
+ index = < 0x00 >;
+ reg = < 0x00 0x1000000 0xffffff >;
+ };
+ };
+
+ chiplet at 2000000 {
+ compatible = "ibm,power9-chiplet";
+ index = < 0x02 >;
+ reg = < 0x00 0x2000000 0xfffff >;
+ };
+
+ chiplet at 3000000 {
+ compatible = "ibm,power9-chiplet";
+ index = < 0x03 >;
+ reg = < 0x00 0x3000000 0xfffff >;
+ };
+
+ chiplet at 4000000 {
+ compatible = "ibm,power9-chiplet";
+ index = < 0x04 >;
+ reg = < 0x00 0x4000000 0xfffff >;
+ };
+
+ chiplet at 5000000 {
+ compatible = "ibm,power9-chiplet";
+ index = < 0x05 >;
+ reg = < 0x00 0x5000000 0xfffff >;
+ };
+
+ chiplet at 6000000 {
+ compatible = "ibm,power9-chiplet";
+ index = < 0x06 >;
+ reg = < 0x00 0x6000000 0xfffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ xbus1_0: xbus at 0 {
+ compatible = "ibm,power9-xbus";
+ index = < 0x00 >;
+ reg = < 0x00 0x6000000 0xffffff >;
+ other-end = "/proc0/pib/chiplet at 6000000/xbus at 0";
+ };
+ };
+
+ chiplet at 7000000 {
+ compatible = "ibm,power9-chiplet";
+ index = < 0x07 >;
+ reg = < 0x00 0x7000000 0xfffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ mc at 0 {
+ compatible = "ibm,power9-mc";
+ index = < 0x00 >;
+ reg = < 0x00 0x7000000 0xffffff >;
+ };
+ };
+
+ chiplet at 8000000 {
+ compatible = "ibm,power9-chiplet";
+ index = < 0x08 >;
+ reg = < 0x00 0x8000000 0xfffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ mc at 1 {
+ compatible = "ibm,power9-mc";
+ index = < 0x01 >;
+ reg = < 0x00 0x8000000 0xffffff >;
+ };
+ };
+
+ chiplet at 9000000 {
+ compatible = "ibm,power9-chiplet";
+ index = < 0x09 >;
+ reg = < 0x00 0x9000000 0xfffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ obus at 0 {
+ compatible = "ibm,power9-obus";
+ index = < 0x00 >;
+ reg = < 0x00 0x9000000 0xffffff >;
+ };
+ };
+
+ chiplet at c000000 {
+ compatible = "ibm,power9-chiplet";
+ index = < 0x0c >;
+ reg = < 0x00 0xc000000 0xfffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ obus at 3 {
+ compatible = "ibm,power9-obus";
+ index = < 0x03 >;
+ reg = < 0x00 0xc000000 0xffffff >;
+ };
+ };
+
+ chiplet at d000000 {
+ compatible = "ibm,power9-chiplet";
+ index = < 0x0d >;
+ reg = < 0x00 0xd000000 0xfffff >;
+ };
+
+ chiplet at e000000 {
+ compatible = "ibm,power9-chiplet";
+ index = < 0x0e >;
+ reg = < 0x00 0xe000000 0xfffff >;
+ };
+
+ chiplet at f000000 {
+ compatible = "ibm,power9-chiplet";
+ index = < 0x0f >;
+ reg = < 0x00 0xf000000 0xfffff >;
+ };
+
+ chiplet at 10000000 {
+ compatible = "ibm,power9-chiplet";
+ index = < 0x10 >;
+ reg = < 0x00 0x10000000 0xfffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ eq at 0 {
+ compatible = "ibm,power9-eq";
+ index = < 0x00 >;
+ reg = < 0x00 0x10000000 0xffffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ ex at 0 {
+ compatible = "ibm,power9-ex";
+ index = < 0x00 >;
+ reg = < 0x00 0x10000000 0xffffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ chiplet at 20000000 {
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+ compatible = "ibm,power9-chiplet";
+ index = < 0x20 >;
+ reg = < 0x00 0x20000000 0xfffff >;
+
+ core at 0 {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x00 >;
+ compatible = "ibm,power9-core";
+ index = < 0x00 >;
+ reg = < 0x00 0x00 0xfffff >;
+
+ thread at 0 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x00 >;
+ index = < 0x00 >;
+ };
+
+ thread at 1 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x01 >;
+ index = < 0x01 >;
+ };
+
+ thread at 2 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x02 >;
+ index = < 0x02 >;
+ };
+
+ thread at 3 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x03 >;
+ index = < 0x03 >;
+ };
+ };
+ };
+
+ chiplet at 21000000 {
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+ compatible = "ibm,power9-chiplet";
+ index = < 0x21 >;
+ reg = < 0x00 0x21000000 0xfffff >;
+
+ core at 0 {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x00 >;
+ compatible = "ibm,power9-core";
+ index = < 0x01 >;
+ reg = < 0x00 0x00 0xfffff >;
+
+ thread at 0 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x00 >;
+ index = < 0x00 >;
+ };
+
+ thread at 1 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x01 >;
+ index = < 0x01 >;
+ };
+
+ thread at 2 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x02 >;
+ index = < 0x02 >;
+ };
+
+ thread at 3 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x03 >;
+ index = < 0x03 >;
+ };
+ };
+ };
+ };
+
+ ex at 1 {
+ compatible = "ibm,power9-ex";
+ index = < 0x01 >;
+ reg = < 0x00 0x10000000 0xffffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ chiplet at 22000000 {
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+ compatible = "ibm,power9-chiplet";
+ index = < 0x22 >;
+ reg = < 0x00 0x22000000 0xfffff >;
+
+ core at 0 {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x00 >;
+ compatible = "ibm,power9-core";
+ index = < 0x02 >;
+ reg = < 0x00 0x00 0xfffff >;
+
+ thread at 0 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x00 >;
+ index = < 0x00 >;
+ };
+
+ thread at 1 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x01 >;
+ index = < 0x01 >;
+ };
+
+ thread at 2 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x02 >;
+ index = < 0x02 >;
+ };
+
+ thread at 3 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x03 >;
+ index = < 0x03 >;
+ };
+ };
+ };
+
+ chiplet at 23000000 {
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+ compatible = "ibm,power9-chiplet";
+ index = < 0x23 >;
+ reg = < 0x00 0x23000000 0xfffff >;
+
+ core at 0 {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x00 >;
+ compatible = "ibm,power9-core";
+ index = < 0x03 >;
+ reg = < 0x00 0x00 0xfffff >;
+
+ thread at 0 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x00 >;
+ index = < 0x00 >;
+ };
+
+ thread at 1 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x01 >;
+ index = < 0x01 >;
+ };
+
+ thread at 2 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x02 >;
+ index = < 0x02 >;
+ };
+
+ thread at 3 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x03 >;
+ index = < 0x03 >;
+ };
+ };
+ };
+ };
+ };
+ };
+
+ chiplet at 11000000 {
+ compatible = "ibm,power9-chiplet";
+ index = < 0x11 >;
+ reg = < 0x00 0x11000000 0xfffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ eq at 1 {
+ compatible = "ibm,power9-eq";
+ index = < 0x01 >;
+ reg = < 0x00 0x11000000 0xffffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ ex at 0 {
+ compatible = "ibm,power9-ex";
+ index = < 0x00 >;
+ reg = < 0x00 0x10000000 0xffffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ chiplet at 24000000 {
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+ compatible = "ibm,power9-chiplet";
+ index = < 0x24 >;
+ reg = < 0x00 0x24000000 0xfffff >;
+
+ core at 0 {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x00 >;
+ compatible = "ibm,power9-core";
+ index = < 0x04 >;
+ reg = < 0x00 0x00 0xfffff >;
+
+ thread at 0 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x00 >;
+ index = < 0x00 >;
+ };
+
+ thread at 1 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x01 >;
+ index = < 0x01 >;
+ };
+
+ thread at 2 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x02 >;
+ index = < 0x02 >;
+ };
+
+ thread at 3 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x03 >;
+ index = < 0x03 >;
+ };
+ };
+ };
+
+ chiplet at 25000000 {
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+ compatible = "ibm,power9-chiplet";
+ index = < 0x25 >;
+ reg = < 0x00 0x25000000 0xfffff >;
+
+ core at 0 {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x00 >;
+ compatible = "ibm,power9-core";
+ index = < 0x05 >;
+ reg = < 0x00 0x00 0xfffff >;
+
+ thread at 0 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x00 >;
+ index = < 0x00 >;
+ };
+
+ thread at 1 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x01 >;
+ index = < 0x01 >;
+ };
+
+ thread at 2 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x02 >;
+ index = < 0x02 >;
+ };
+
+ thread at 3 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x03 >;
+ index = < 0x03 >;
+ };
+ };
+ };
+ };
+
+ ex at 1 {
+ compatible = "ibm,power9-ex";
+ index = < 0x01 >;
+ reg = < 0x00 0x10000000 0xffffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ chiplet at 26000000 {
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+ compatible = "ibm,power9-chiplet";
+ index = < 0x26 >;
+ reg = < 0x00 0x26000000 0xfffff >;
+
+ core at 0 {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x00 >;
+ compatible = "ibm,power9-core";
+ index = < 0x06 >;
+ reg = < 0x00 0x00 0xfffff >;
+
+ thread at 0 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x00 >;
+ index = < 0x00 >;
+ };
+
+ thread at 1 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x01 >;
+ index = < 0x01 >;
+ };
+
+ thread at 2 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x02 >;
+ index = < 0x02 >;
+ };
+
+ thread at 3 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x03 >;
+ index = < 0x03 >;
+ };
+ };
+ };
+
+ chiplet at 27000000 {
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+ compatible = "ibm,power9-chiplet";
+ index = < 0x27 >;
+ reg = < 0x00 0x27000000 0xfffff >;
+
+ core at 0 {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x00 >;
+ compatible = "ibm,power9-core";
+ index = < 0x07 >;
+ reg = < 0x00 0x00 0xfffff >;
+
+ thread at 0 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x00 >;
+ index = < 0x00 >;
+ };
+
+ thread at 1 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x01 >;
+ index = < 0x01 >;
+ };
+
+ thread at 2 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x02 >;
+ index = < 0x02 >;
+ };
+
+ thread at 3 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x03 >;
+ index = < 0x03 >;
+ };
+ };
+ };
+ };
+ };
+ };
+
+ chiplet at 12000000 {
+ compatible = "ibm,power9-chiplet";
+ index = < 0x12 >;
+ reg = < 0x00 0x12000000 0xfffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ eq at 2 {
+ compatible = "ibm,power9-eq";
+ index = < 0x02 >;
+ reg = < 0x00 0x12000000 0xffffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ ex at 0 {
+ compatible = "ibm,power9-ex";
+ index = < 0x00 >;
+ reg = < 0x00 0x12000000 0xffffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ chiplet at 28000000 {
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+ compatible = "ibm,power9-chiplet";
+ index = < 0x28 >;
+ reg = < 0x00 0x28000000 0xfffff >;
+
+ core at 0 {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x00 >;
+ compatible = "ibm,power9-core";
+ index = < 0x08 >;
+ reg = < 0x00 0x00 0xfffff >;
+
+ thread at 0 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x00 >;
+ index = < 0x00 >;
+ };
+
+ thread at 1 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x01 >;
+ index = < 0x01 >;
+ };
+
+ thread at 2 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x02 >;
+ index = < 0x02 >;
+ };
+
+ thread at 3 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x03 >;
+ index = < 0x03 >;
+ };
+ };
+ };
+
+ chiplet at 29000000 {
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+ compatible = "ibm,power9-chiplet";
+ index = < 0x29 >;
+ reg = < 0x00 0x29000000 0xfffff >;
+
+ core at 0 {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x00 >;
+ compatible = "ibm,power9-core";
+ index = < 0x09 >;
+ reg = < 0x00 0x00 0xfffff >;
+
+ thread at 0 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x00 >;
+ index = < 0x00 >;
+ };
+
+ thread at 1 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x01 >;
+ index = < 0x01 >;
+ };
+
+ thread at 2 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x02 >;
+ index = < 0x02 >;
+ };
+
+ thread at 3 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x03 >;
+ index = < 0x03 >;
+ };
+ };
+ };
+ };
+
+ ex at 1 {
+ compatible = "ibm,power9-ex";
+ index = < 0x01 >;
+ reg = < 0x00 0x12000000 0xffffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ chiplet at 2a000000 {
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+ compatible = "ibm,power9-chiplet";
+ index = < 0x2a >;
+ reg = < 0x00 0x2a000000 0xfffff >;
+
+ core at 0 {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x00 >;
+ compatible = "ibm,power9-core";
+ index = < 0x0a >;
+ reg = < 0x00 0x00 0xfffff >;
+
+ thread at 0 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x00 >;
+ index = < 0x00 >;
+ };
+
+ thread at 1 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x01 >;
+ index = < 0x01 >;
+ };
+
+ thread at 2 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x02 >;
+ index = < 0x02 >;
+ };
+
+ thread at 3 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x03 >;
+ index = < 0x03 >;
+ };
+ };
+ };
+
+ chiplet at 2b000000 {
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+ compatible = "ibm,power9-chiplet";
+ index = < 0x2b >;
+ reg = < 0x00 0x2b000000 0xfffff >;
+
+ core at 0 {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x00 >;
+ compatible = "ibm,power9-core";
+ index = < 0x0b >;
+ reg = < 0x00 0x00 0xfffff >;
+
+ thread at 0 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x00 >;
+ index = < 0x00 >;
+ };
+
+ thread at 1 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x01 >;
+ index = < 0x01 >;
+ };
+
+ thread at 2 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x02 >;
+ index = < 0x02 >;
+ };
+
+ thread at 3 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x03 >;
+ index = < 0x03 >;
+ };
+ };
+ };
+ };
+ };
+ };
+
+ chiplet at 13000000 {
+ compatible = "ibm,power9-chiplet";
+ index = < 0x13 >;
+ reg = < 0x00 0x13000000 0xfffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ eq at 3 {
+ compatible = "ibm,power9-eq";
+ index = < 0x03 >;
+ reg = < 0x00 0x13000000 0xffffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ ex at 0 {
+ compatible = "ibm,power9-ex";
+ index = < 0x00 >;
+ reg = < 0x00 0x13000000 0xffffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ chiplet at 2c000000 {
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+ compatible = "ibm,power9-chiplet";
+ index = < 0x2c >;
+ reg = < 0x00 0x2c000000 0xfffff >;
+
+ core at 0 {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x00 >;
+ compatible = "ibm,power9-core";
+ index = < 0x0c >;
+ reg = < 0x00 0x00 0xfffff >;
+
+ thread at 0 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x00 >;
+ index = < 0x00 >;
+ };
+
+ thread at 1 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x01 >;
+ index = < 0x01 >;
+ };
+
+ thread at 2 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x02 >;
+ index = < 0x02 >;
+ };
+
+ thread at 3 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x03 >;
+ index = < 0x03 >;
+ };
+ };
+ };
+
+ chiplet at 2d000000 {
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+ compatible = "ibm,power9-chiplet";
+ index = < 0x2d >;
+ reg = < 0x00 0x2d000000 0xfffff >;
+
+ core at 0 {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x00 >;
+ compatible = "ibm,power9-core";
+ index = < 0x0d >;
+ reg = < 0x00 0x00 0xfffff >;
+
+ thread at 0 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x00 >;
+ index = < 0x00 >;
+ };
+
+ thread at 1 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x01 >;
+ index = < 0x01 >;
+ };
+
+ thread at 2 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x02 >;
+ index = < 0x02 >;
+ };
+
+ thread at 3 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x03 >;
+ index = < 0x03 >;
+ };
+ };
+ };
+ };
+
+ ex at 1 {
+ compatible = "ibm,power9-ex";
+ index = < 0x01 >;
+ reg = < 0x00 0x13000000 0xffffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ chiplet at 2e000000 {
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+ compatible = "ibm,power9-chiplet";
+ index = < 0x2e >;
+ reg = < 0x00 0x2e000000 0xfffff >;
+
+ core at 0 {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x00 >;
+ compatible = "ibm,power9-core";
+ index = < 0x0e >;
+ reg = < 0x00 0x00 0xfffff >;
+
+ thread at 0 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x00 >;
+ index = < 0x00 >;
+ };
+
+ thread at 1 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x01 >;
+ index = < 0x01 >;
+ };
+
+ thread at 2 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x02 >;
+ index = < 0x02 >;
+ };
+
+ thread at 3 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x03 >;
+ index = < 0x03 >;
+ };
+ };
+ };
+
+ chiplet at 2f000000 {
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+ compatible = "ibm,power9-chiplet";
+ index = < 0x2f >;
+ reg = < 0x00 0x2f000000 0xfffff >;
+
+ core at 0 {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x00 >;
+ compatible = "ibm,power9-core";
+ index = < 0x0f >;
+ reg = < 0x00 0x00 0xfffff >;
+
+ thread at 0 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x00 >;
+ index = < 0x00 >;
+ };
+
+ thread at 1 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x01 >;
+ index = < 0x01 >;
+ };
+
+ thread at 2 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x02 >;
+ index = < 0x02 >;
+ };
+
+ thread at 3 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x03 >;
+ index = < 0x03 >;
+ };
+ };
+ };
+ };
+ };
+ };
+
+ chiplet at 14000000 {
+ compatible = "ibm,power9-chiplet";
+ index = < 0x14 >;
+ reg = < 0x00 0x14000000 0xfffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ eq at 4 {
+ compatible = "ibm,power9-eq";
+ index = < 0x04 >;
+ reg = < 0x00 0x13000000 0xffffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ ex at 0 {
+ compatible = "ibm,power9-ex";
+ index = < 0x00 >;
+ reg = < 0x00 0x14000000 0xffffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ chiplet at 30000000 {
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+ compatible = "ibm,power9-chiplet";
+ index = < 0x30 >;
+ reg = < 0x00 0x30000000 0xfffff >;
+
+ core at 0 {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x00 >;
+ compatible = "ibm,power9-core";
+ index = < 0x10 >;
+ reg = < 0x00 0x00 0xfffff >;
+
+ thread at 0 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x00 >;
+ index = < 0x00 >;
+ };
+
+ thread at 1 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x01 >;
+ index = < 0x01 >;
+ };
+
+ thread at 2 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x02 >;
+ index = < 0x02 >;
+ };
+
+ thread at 3 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x03 >;
+ index = < 0x03 >;
+ };
+ };
+ };
+
+ chiplet at 31000000 {
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+ compatible = "ibm,power9-chiplet";
+ index = < 0x31 >;
+ reg = < 0x00 0x31000000 0xfffff >;
+
+ core at 0 {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x00 >;
+ compatible = "ibm,power9-core";
+ index = < 0x11 >;
+ reg = < 0x00 0x00 0xfffff >;
+
+ thread at 0 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x00 >;
+ index = < 0x00 >;
+ };
+
+ thread at 1 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x01 >;
+ index = < 0x01 >;
+ };
+
+ thread at 2 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x02 >;
+ index = < 0x02 >;
+ };
+
+ thread at 3 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x03 >;
+ index = < 0x03 >;
+ };
+ };
+ };
+ };
+
+ ex at 1 {
+ compatible = "ibm,power9-ex";
+ index = < 0x01 >;
+ reg = < 0x00 0x14000000 0xffffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ chiplet at 32000000 {
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+ compatible = "ibm,power9-chiplet";
+ index = < 0x32 >;
+ reg = < 0x00 0x32000000 0xfffff >;
+
+ core at 0 {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x00 >;
+ compatible = "ibm,power9-core";
+ index = < 0x12 >;
+ reg = < 0x00 0x00 0xfffff >;
+
+ thread at 0 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x00 >;
+ index = < 0x00 >;
+ };
+
+ thread at 1 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x01 >;
+ index = < 0x01 >;
+ };
+
+ thread at 2 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x02 >;
+ index = < 0x02 >;
+ };
+
+ thread at 3 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x03 >;
+ index = < 0x03 >;
+ };
+ };
+ };
+
+ chiplet at 33000000 {
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+ compatible = "ibm,power9-chiplet";
+ index = < 0x33 >;
+ reg = < 0x00 0x33000000 0xfffff >;
+
+ core at 0 {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x00 >;
+ compatible = "ibm,power9-core";
+ index = < 0x13 >;
+ reg = < 0x00 0x00 0xfffff >;
+
+ thread at 0 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x00 >;
+ index = < 0x00 >;
+ };
+
+ thread at 1 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x01 >;
+ index = < 0x01 >;
+ };
+
+ thread at 2 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x02 >;
+ index = < 0x02 >;
+ };
+
+ thread at 3 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x03 >;
+ index = < 0x03 >;
+ };
+ };
+ };
+ };
+ };
+ };
+
+ chiplet at 15000000 {
+ compatible = "ibm,power9-chiplet";
+ index = < 0x15 >;
+ reg = < 0x00 0x15000000 0xfffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ eq at 5 {
+ compatible = "ibm,power9-eq";
+ index = < 0x05 >;
+ reg = < 0x00 0x13000000 0xffffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ ex at 0 {
+ compatible = "ibm,power9-ex";
+ index = < 0x00 >;
+ reg = < 0x00 0x15000000 0xffffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ chiplet at 34000000 {
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+ compatible = "ibm,power9-chiplet";
+ index = < 0x34 >;
+ reg = < 0x00 0x34000000 0xfffff >;
+
+ core at 0 {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x00 >;
+ compatible = "ibm,power9-core";
+ index = < 0x14 >;
+ reg = < 0x00 0x00 0xfffff >;
+
+ thread at 0 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x00 >;
+ index = < 0x00 >;
+ };
+
+ thread at 1 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x01 >;
+ index = < 0x01 >;
+ };
+
+ thread at 2 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x02 >;
+ index = < 0x02 >;
+ };
+
+ thread at 3 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x03 >;
+ index = < 0x03 >;
+ };
+ };
+ };
+
+ chiplet at 35000000 {
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+ compatible = "ibm,power9-chiplet";
+ index = < 0x35 >;
+ reg = < 0x00 0x35000000 0xfffff >;
+
+ core at 0 {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x00 >;
+ compatible = "ibm,power9-core";
+ index = < 0x15 >;
+ reg = < 0x00 0x00 0xfffff >;
+
+ thread at 0 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x00 >;
+ index = < 0x00 >;
+ };
+
+ thread at 1 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x01 >;
+ index = < 0x01 >;
+ };
+
+ thread at 2 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x02 >;
+ index = < 0x02 >;
+ };
+
+ thread at 3 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x03 >;
+ index = < 0x03 >;
+ };
+ };
+ };
+ };
+
+ ex at 1 {
+ compatible = "ibm,power9-ex";
+ index = < 0x01 >;
+ reg = < 0x00 0x15000000 0xffffff >;
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+
+ chiplet at 36000000 {
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+ compatible = "ibm,power9-chiplet";
+ index = < 0x36 >;
+ reg = < 0x00 0x36000000 0xfffff >;
+
+ core at 0 {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x00 >;
+ compatible = "ibm,power9-core";
+ index = < 0x16 >;
+ reg = < 0x00 0x00 0xfffff >;
+
+ thread at 0 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x00 >;
+ index = < 0x00 >;
+ };
+
+ thread at 1 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x01 >;
+ index = < 0x01 >;
+ };
+
+ thread at 2 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x02 >;
+ index = < 0x02 >;
+ };
+
+ thread at 3 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x03 >;
+ index = < 0x03 >;
+ };
+ };
+ };
+
+ chiplet at 37000000 {
+ #address-cells = < 0x02 >;
+ #size-cells = < 0x01 >;
+ compatible = "ibm,power9-chiplet";
+ index = < 0x37 >;
+ reg = < 0x00 0x37000000 0xfffff >;
+
+ core at 0 {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x00 >;
+ compatible = "ibm,power9-core";
+ index = < 0x17 >;
+ reg = < 0x00 0x00 0xfffff >;
+
+ thread at 0 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x00 >;
+ index = < 0x00 >;
+ };
+
+ thread at 1 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x01 >;
+ index = < 0x01 >;
+ };
+
+ thread at 2 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x02 >;
+ index = < 0x02 >;
+ };
+
+ thread at 3 {
+ compatible = "ibm,power9-thread";
+ reg = < 0x00 >;
+ tid = < 0x03 >;
+ index = < 0x03 >;
+ };
+ };
+ };
+ };
+ };
+ };
+ };
+ };
+};
--
2.21.0
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